Rectilinear Steiner trees with minimum Elmore delay

Abstract

We provide a new theoretical framework for constructing Steiner routing trees with minimum Elmore delay. Earlier work [3,13] has established Elmore delay as a high delity estimate of \physical", i.e., SPICEcomputed, signal delay. Previously, however, it was not known how to construct an Elmore delay-optimal Steiner tree. Our main theoretical result is a generalization of Hanan's theorem [11] which limited the number of possible locations of Steiner nodes in an optimal delay rectilinear Steiner tree. Another theoretical result establishes a new decomposition theorem for constructing optimal-delay Steiner trees. We develop a branch-andbound method, called BB-SORT-C, which exactly minimizes any linear combination of Elmore sink delays; BB-SORT-C is practical for routing small nets and for delimiting the space of achievable routing solutions with respect to Elmore delay.

Combinatorial Problems in Chip Design

“…The problem is known to be NP-hard (Boese et al [1994]). For |T | = 1 it is trivial; a shortest path does the job.…”

“…But even for |T | = 2 there are instances in which the only optimal solution is not part of the Hanan grid, the grid of horizontal and vertical lines induced by the source and the sinks (Boese et al [1994]). This is not true for the variant in which t∈T a t ED(s, t) is minimized for weights a t > 0 (t ∈ T ); hence this variant can be solved in exponential time.…”

Timing-Driven Interconnect Synthesis

“…problem [8], and provided efficient heuristics that combine Steiner construction, delay estimation, and global slack removal [10].…”

“…For example, an early sequence of papers by Boese, Kahng, and Robins [7,8,9,10] proposed new classes of delay objectives, along with improved-performance routing algorithms that directly optimized, e.g., the Elmore delay. These works also established the fidelity of Elmore-based constructions relative to accurate delay simulators (e.g., SPICE) [62].…”

Simultaneous Gate and Interconnect Sizing for Circuit-Level Delay Optimization

“…Several algorithms for optimal interconnect tree design have also been proposed in the literature with the more recent ones attempting to minimize the delay at the sinks [6] instead of minimizing the length of the interconnect branches in the tree [7]. Recently, recognizing that large reductions in interconnect delay can be achieved by selectively widening the branches of the interconnect tree (wiresizing), algorithms for optimal wiresizing have been proposed in [1,8,9].…”