Reconfigurable STT-NV LUT-based functional units to improve performance in general-purpose processors

Abstract

Unavailability of functional units is a major performance bottleneck in general-purpose processors (GPP). In a GPP with limited number of functional units while a functional unit may be heavily utilized at times, creating a performance bottleneck, the other functional units might be under-utilized. We propose a novel idea for adapting functional units in GPP architecture in order to overcome this challenge. For this purpose, a selected set of complex functional units that might be under-utilized such as multiplier and divider, are realized using a programmable look up table-based fabric. This allows for run-time adaptation of functional units to improving performance. The programmable look up tables are realized using magnetic tunnel junction (MTJ) based memories that dissipate near zero leakage and are CMOS compatible. We have applied this idea to a dual issue architecture. The results show that compared to a design with all CMOS functional units a performance improvement of 18%, on average is achieved for standard benchmarks. This comes with 4.1% power increase in integer benchmarks and 2.3% power decrease in floating point benchmarks, compared to a CMOS design.

Designing an Efficient Hardware Accelerator for Data Sorting Integrated With a Risc-V

“…Some of the efficient soft core processors are SecretBlaze [8] and Chisel [9]. Conventional reconfigurable architectures have some drawbacks like application domain is not generic, power inefficient [10]- [13]. [7] proposes a reconfigurable architecture focusing on efficient area and power for soft core processors by making use of low utilization and fragmented functional units.…”

Preventing design reverse engineering with reconfigurable spin transfer torque LUT gates

“…Table 1 shows the characterization of STT-LUTs with fan-ins ranging from 2 to 8. With increase in fan-in the active power and delay generally increase, but the leakage power remains very low and almost insensitive to the fan-in, since the leakage is limited by the stacking effect, and saturated through the NMOS pulldown network gated by the clocked transistor in the dynamic current source (Figure 1) [13,16]. Table 2 shows the simulation results of the STT-LUT and static custom CMOS circuit styles for logic gates of various complexity implemented in a predictive 32nm technology.…”

Reliability analysis of spin transfer torque based look up tables under process variations and NBTI aging

“…Due to its non-volatile nature and CMOS compatibility, STT-based memory (STT-RAM) has shown great promise in addressing the leakage barrier for SRAM. While the high write power still remains to be a major obstacle for STTRAM [3], the application of STT-based memory in reconfigurable logic, as in Field Programmable Gate Arrays (FPGA) or reconfigurable functional units, seems more promising due to the low frequency of reconfiguration where the write power occurs [4,25,26]. Reconfigurable logic relies on implementing logic in small Look-Up- Tables (LUT).…”