Preventing design reverse engineering with reconfigurable spin transfer torque LUT gates

Abstract

This paper presents a rigorous step towards design-for-assurance by employing the non-volatile spin transfer torque magnetic technology to design reconfigurable Look-Up-Tables logic components (NV-STT-based LUTs). Further, we introduce a novel security-driven STT-CMOS hybrid design flow that ensures the functionality of NV-STT-based LUTs cannot be determined in any manageable time, rendering any design reverse engineering attack ineffective. In addition, the flow ensures that there is minimum or no impact on design parametric constraints including performance, power and area.

Hybrid Obfuscation Technique to Protect Source Code From Prohibited Software Reverse Engineering

“…Anti-reverse engineering techniques are going towards obfuscation due to its power to transform the code into different presentations. Obfuscation opens a room for innovation where the developer can use different languages in programming, a language that only the owner can understand what it is and what it does [14]. Obfuscation consists of code transformations that make a program more difficult to understand by changing its structure [15].…”

Engaging Undergraduate Students in Research: Efficient Logic Design in Nano-Scale using Spin Transfer Torque Memory Technology

“…An STT-LUT is composed of a number MTJs for storing the hardware configuration state and a multiplexers (MUX) for selecting a unique MTS state to be read out (see Figure 2) [6][7]. A MUX is a combinational circuit in which a set of selection inputs determines a specific input signal to be selected as output signal [8].…”

“…To find the best combination, three selection algorithms were used to determine which set of gates should be mapped. The algorithms are independent selection, dependent selection, and parametric-aware dependent selection [7].…”

“…An attacker can potentially decrypt the function of the LUT by simply using trial and error; this is known as the brute force method. This is possible due to the fact that the preceding and subsequent gates of the LUT is not mapped, giving the attacker an idea of what kind of function the LUT might hold [7].…”

“…Since the mapped gates are along the same pathways, this method could result in more speed penalty as the cascaded LUT delays add up. This selection trades speed for security [7].…”