Comparative analysis of hybrid Magnetic Tunnel Junction and CMOS logic circuits

Almasi, Darya; Homayoun, Houman; Salmani, Hassan; Mahmoodi, Hamid

doi:10.1109/socc.2016.7905481

Cited by 4 publications

(2 citation statements)

References 7 publications

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“…Most of the STT-MTJs' TMR ratios are in the range of 100%-200%. 25) Meanwhile, the voltage scaling of MOSFETs limits the maximum resistance of STT-MTJ. A large resistance of the STT-MTJ with a large TMR ratio makes its switching difficult at a small voltage in scaled CMOS circuits.…”

Section: Stt-mtj Based Synapsementioning

confidence: 99%

A binarized spiking neural network based on auto-reset LIF neurons and large signal synapses using STT-MTJs

Liu

Ohsawa

2023

Jpn. J. Appl. Phys.

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A binarized spiking neural network using auto-reset leaky integrate-and-fire (LIF) neurons with a two-transistor and three-magnetic tunnel junction (2T3MTJ) core and large signal synapses with two-transistor and two-magnetic tunnel junction (2T2MTJ) is designed. The network is applied to a classifier of the MNIST handwritten digit dataset with a 784×400 synapse crossbar array. The weights are trained offline by using the spike-timing-dependent plasticity (STDP) learning algorithm and deployed to the spin-transfer torque magnetic tunnel junction (STT-MTJ) resistances in the synapses after being binarized. Its performance is evaluated by HSPICE using the STT-MTJ device model which takes stochastic change in the angle between the two magnetic moments in the free and the pinned layers into consideration. 75% test accuracy is achieved for 1200 patterns with 1ns read and 1ns write operations and 0.23pJ/SOP energy consumption.

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Section: Stt-mtj Based Synapsementioning

confidence: 99%

A binarized spiking neural network based on auto-reset LIF neurons and large signal synapses using STT-MTJs

Liu

Ohsawa

2023

Jpn. J. Appl. Phys.

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“…We investigate various methods of mapping a partial set of logic gate to STT-LUTs in an adder benchmark circuit. In this approach the design will utilize a hybrid of custom and reconfigurable logic components [9]. Fig.…”

Section: Case Study: Stt-lut Mapping On Adder Circuitmentioning

confidence: 99%