Reconfigurable multi-mode sigma–delta modulator for 4G mobile terminals

Silva, Artur M. S.; Guilherme, Jorge; Horta, Nuno

doi:10.1016/j.vlsi.2008.07.004

Cited by 29 publications

(8 citation statements)

References 34 publications

(54 reference statements)

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“…Therefore, according to the literature, we fix some standards summarized in Tab. 1 [19][20][21]. During this phase, to project some FF ΔΣ modulators performance predictions for low power systems, we choose a decreasing power consumption estimated less than 1mW and a variable F S using future CMOS process (Tab.…”

Section: Prediction Of Ff δ σ Modulator Performance Through Maple Toolmentioning

confidence: 99%

A ΔΣ Modulator Automated Synthesis Tool for Wireless Standards

2018

Teh. vjesn.

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This paper presents the prediction of single-bit discrete-time feed-forward Delta-Sigma (DT FF ΔΣ) modulators performance for wireless standards with the use of two methods. The presented work uses the MAPLE tool and a new design automation tool to estimate the performance of different DT FF ΔΣ modulators topologies intended for low power consumption systems. The proposed tool is based on synthesis algorithm, which takes advantage of analytical models of both FF ΔΣ modulator and operational transconductance amplifier (OTA) performance. By defining the required specifications, the proposed synthesis tool is capable to find the predictive performance of both the modulator topology and the required OTA building block for future process. A Graphical User Interface is programmed to easily present some designed circuits examples.

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Section: Prediction Of Ff δ σ Modulator Performance Through Maple Toolmentioning

confidence: 99%

A ΔΣ Modulator Automated Synthesis Tool for Wireless Standards

2018

Teh. vjesn.

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“…Authors in [12] presented the concepts in the design of clock circuitry for high-speed ADCs. Timing jitter and quantization error effect the performance of ADC in SDR receivers, which is explained in [13]. Band pass sampling for down conversion of a few RF signals is given in [14].…”

Section: Introductionmentioning

confidence: 99%

Universal Band Pass Sampling Algorithm for Integration of Multiple Wireless Technologies Using Software Defined Radio Platform

Budaraju¹,

Anjaneyulu²

2016

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Software Defined Radio (SDR) architecture allows us to integrate different mobile technologies using common hardware but with different software modules. To achieve this, we need to keep the signal in digital form for as much portion of the circuitry as possible, so that the implementation could be carried out by programmable digital processors. For this purpose, the incoming radio frequency (RF) signal is down converted to baseband spectrum using band pass sampling method. Research works carried out so far in this field have developed a few algorithms for band pass sampling. But, these algorithms are not much useful for most of the mobile communication systems and they use complex methodology for computing the sampling frequency values. In order to use the SDR platform to integrate all current wireless technologies, an efficient, cost effective and less complex algorithm that can be labelled as universal band pass sampling algorithm is developed in this paper for multiple mobile systems. This algorithm is based on a novel idea of inserting guard bands between the signals which reduces the design complexities of perfect ADC and sharp cut off filters. Using this algorithm, valid sampling frequency ranges and corresponding IF values are calculated for down converting RF signals. The algorithm is tested for six RF signals of different wireless technologies which are integrated and simultaneously down converted using SDR based front end receiver and thus the system multiplies the base station capacity by a factor of six. The simulation results are obtained and shown in this paper which proves that the algorithm developed works well for most of the wireless technologies.

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“…A high resolution high speed ADC will only allow the shifting of several RF and analog processing to the digital domain in order to provide more flexibility and increase the design complexity [5]. The use of ΔΣ modulators in multistandard receivers is suitable for several reasons among which we can cite, firstly, that ΣΔ modulators are very linear and are also less sensitive to circuit non-idealities than other types of data converters [6]. Secondly, the noise shaping and the oversampling performed by ΣΔ modulators allow to achieve high Dynamic Range (DR) for narrow bandwidths and lower DR for higher bandwidths.…”

Section: Introductionmentioning

confidence: 99%

Behavioral Modeling and Simulation of Cascade Multibit ΣΔ Modulator for Multistandard Radio Receiver

Zouari¹,

Daoud²,

Loulou³

et al. 2013

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In this paper, a cascade Sigma-Delta (ΣΔ) Analog to Digital Converter (ADC) for multistandard radio receiver was presented. This converter is supposed to be able to support GSM, UMTS, Wifi and WiMAX communication standards. The Sigma-Delta modulator makes use of 4 bit quantizer and Data-Weighted-Averaging (DWA) technique to attain high linearity over a wide bandwidth. A top-down design methodology was adopted to provide a reliable tool for the design of reconfigurable high-speed ΣΔMs. VHDL-AMS language was used to model the analog and mixed parts of the selected 2-1-1 cascade ΣΔ converter and to verify their reconfiguration parameters based on behavioural simulation. This multistandard architecture was high level sized to adapt the modulator performance to the different standards requirements. The effects of circuit non-idealities on the modulator performance were modeled and analyzed in VHDLAMS to extract the required circuit parameters.

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Reconfigurable multi-mode sigma–delta modulator for 4G mobile terminals

Cited by 29 publications

References 34 publications

A ΔΣ Modulator Automated Synthesis Tool for Wireless Standards

A ΔΣ Modulator Automated Synthesis Tool for Wireless Standards

Universal Band Pass Sampling Algorithm for Integration of Multiple Wireless Technologies Using Software Defined Radio Platform

Behavioral Modeling and Simulation of Cascade Multibit ΣΔ Modulator for Multistandard Radio Receiver

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