Behavioral Modeling and Simulation of Cascade Multibit ΣΔ Modulator for Multistandard Radio Receiver

Abstract

<p align="justify"> <span>In<i> </i>this paper, a cascade Sigma-Delta (ΣΔ) Analog to Digital Converter (ADC) for multistandard radio receiver was presented.</span><span> </span><span>This converter is supposed to be able to support GSM, UMTS, Wifi and WiMAX communication standards.</span><span> The Sigma-Delta modulator makes use of 4 bit quantizer and Data-Weighted-Averaging (DWA) technique to attain high linearity over a wide bandwidth. </span><span>A top-down design methodology was adopted to provide a reliable tool for the design of reconfigurable high-speed ΣΔMs. VHDL-AMS language was used to model the analog and mixed parts of the selected 2-1-1 cascade ΣΔ converter and to verify their reconfiguration parameters based on behavioural simulation. This multistandard architecture was high level sized to adapt the modulator performance to the different standards requirements. </span><span>The effects of circuit non-idealities on the modulator performance were modeled and analyzed in VHDLAMS to extract the required circuit parameters.</span><span></span> </p> <p> <span></span> </p