Reconfigurable ECO Cells for Timing Closure and IR Drop Minimization

Chen, Hsien‐Te; Chang, Chieh-Chun; Hwang, TingTing

doi:10.1109/tvlsi.2009.2026478

Cited by 13 publications

(5 citation statements)

References 6 publications

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“…S1) . In addition, recongfigurable gates can be deployed in chips to tackle Engineering Change Orders (ECO) 39 , 40 , where functional logic changes need to be met with minimal layout changes. The ability to meet functional changes with existing gates in the design is relevant for both pre-mask and post-mask ECOs.…”

Section: Introductionmentioning

confidence: 99%

Hardware functional obfuscation with ferroelectric active interconnects

Deng

et al. 2022

Nat Commun

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Existing circuit camouflaging techniques to prevent reverse engineering increase circuit-complexity with significant area, energy, and delay penalty. In this paper, we propose an efficient hardware encryption technique with minimal complexity and overheads based on ferroelectric field-effect transistor (FeFET) active interconnects. By utilizing the threshold voltage programmability of the FeFETs, run-time reconfigurable inverter-buffer logic, utilizing two FeFETs and an inverter, is enabled. Judicious placement of the proposed logic makes it act as a hardware encryption key and enable encoding and decoding of the functional output without affecting the critical path timing delay. Additionally, a peripheral programming scheme for reconfigurable logic by reusing the existing scan chain logic is proposed, obviating the need for specialized programming logic and circuitry for keybit distribution. Our analysis shows an average encryption probability of 97.43% with an increase of 2.24%/ 3.67% delay for the most critical path/ sum of 100 critical paths delay for ISCAS85 benchmarks.

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Section: Introductionmentioning

confidence: 99%

Hardware functional obfuscation with ferroelectric active interconnects

Deng

et al. 2022

Nat Commun

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“…S1). In addition, recongfigurable gates can be deployed in chips to tackle Engineering Change Orders (ECO) 37,38 , where functional logic changes need to be met with minimal layout changes. The ability to meet functional changes with existing gates in the design is relevant for both pre-mask and post-mask ECOs.…”

Section: Introductionmentioning

confidence: 99%

Hardware Functional Obfuscation With Ferroelectric Active Interconnects

Yu,

Xu,

Deng

et al. 2021

Preprint

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Camouflaging gate techniques are typically used in hardware security to prevent reverse engineering. Layout level camouflaging by adding dummy contacts ensures some level of protection against extracting the correct netlist. Threshold voltage manipulation for multifunctional logic with identical layouts has also been introduced for functional obfuscation. All these techniques are implemented at the expense of circuit-complexity and with significant area, energy, and delay penalty. In this paper, we propose an efficient hardware encryption technique with minimal complexity and overheads based on ferroelectric field-effect transistor (FeFET) active interconnects. The active interconnect provides run-time reconfigurable inverter-buffer logic by utilizing the threshold voltage programmability of the FeFETs. Our method utilizes only two FeFETs and an inverter to realize the masking function compared to recent reconfigurable logic gate implementations using several FeFETs and complex differential logic. We fabricate the proposed circuit and demonstrate the functionality. Judicious placement of the proposed logic in the IC makes it acts as a hardware encryption key and

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“…These incremental changes can be functional ECO, dedicated for functional rectification or specification modification, or timing ECO, dedicated for timing closure and optimization. Recently, metal-only ECO has drawn great attentions in literature, e.g., [2,3,4,5,6,7,8,9,10,11,12,13]. To enable metal-only ECO, (redundant) spare cells are inserted at the early placement and routing stage.…”

Section: Introductionmentioning

confidence: 99%

“…Initially, S 1 has 3 free tiles and can implement every cell type listed in Fig. 1 ing spare arrays [12,13]. In addition to timing ECO, spare arrays are also suitable for functional ECO because of their versatile functionality.…”

Section: Introductionmentioning

confidence: 99%

Functional ECO Using Metal-Configurable Gate-Array Spare Cells

Chang

Jiang

Chang

2014

Proceedings of the 51st Annual Design Automation Conference

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Metal-configurable gate-array spare cells, which have versatile functionality, are developed to overcome the inflexibility of standard spare cells used in conventional metal-only engineering change order (ECO). In this paper, we focus on functional ECO optimization using the new type of spare cells to fully exploit its strength. We observe that this functional ECO problem has the nature of dynamic logical and physical costs for selecting spare gate arrays. Unlike existing functional ECO works, which perform technology mapping based on ECO patches, we perform reverse mapping from spare gate arrays to handle these dynamic costs. We devise a spare array relation graph to record geometrical adjacency among spare gate arrays and interleave with the and-inverter network of ECO patches. To avoid redundant traversal and monitor the dynamic costs, we adopt A* search to simultaneously traverse and map between the logical ECO network and the physical spare array relation graph.

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Reconfigurable ECO Cells for Timing Closure and IR Drop Minimization

Cited by 13 publications

References 6 publications

Hardware functional obfuscation with ferroelectric active interconnects

Hardware functional obfuscation with ferroelectric active interconnects

Hardware Functional Obfuscation With Ferroelectric Active Interconnects

Functional ECO Using Metal-Configurable Gate-Array Spare Cells

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