Recent progress in deep-depletion diamond metal–oxide–semiconductor field-effect transistors

Abstract

Diamond has been explored to develop prototype field-effect transistors (FETs). At present, various architectures that are suited to high temperature and high-radiation environments are still under investigation for power electronics applications. Recently, the deep-depletion diamond metal–oxide–semiconductor FET (D3MOSFET) concept has been introduced and demonstrated to be a good candidate for designing efficient diamond MOSFETs. In this paper, a general introduction to the concept of deep depletion is given. The key issues concerning the design and fabrication of this kind of diamond MOSFET are then described and discussed in terms of quasi static performance (the ‘on’ and ‘off’ states). A demonstration of the working regimes of a fabricated normally-on D3MOSFET is described, which reached a critical field of at least 5.4 MV cm−1 at a drain–source bias of −175 V, without electric field relaxation structures. The minimum on-state resistance was measured and found to be R ON,S = 50 mΩ cm2 at 250 ∘C. Finally, the D3MOSFET is contextualized as part of a global research effort to develop diamond power FETs. Some of the main challenges regarding the fabrication of competitive D3MOSFETs and, more generally, diamond power devices are discussed.

Non‐Volatile Photo‐Switch Using a Diamond pn Junction

“…The threshold voltage should be reduced in a future work while optimizing the threshold voltage vs. ON‐state resistance trade‐off, as presented for example for lateral diamond MOS‐gated FET in ref. [23]. The gate recess architecture has proven to be an efficient way to combine a lower threshold voltage with a low on state resistance, as presented for lateral GaN FETs [ 24 ] or in early works with diamond lateral FETs.…”

“…The detailed process is given in ref. [23]. The back contact between the substrate and the gold layer on the alumina plate was done thanks to silver paste.…”

Analytic modeling of a hybrid power module based on diamond and SiC devices

“…Furthermore, parasitic capacitances between each device terminals can be observed which induces switching losses due to the commutation time between two states (ON/OFF or OFF/ON). The calculations of both losses type are based on several assumptions which are key parameters to design and size the power devices: the device is of vertical type, and the conduction losses are only due to the drift region [25]; the drift region is considered in Non-Punch Through (NPT) configuration, which maximizes the doping density of the drift layer and reduces the device on-state resistance [20]; the turn off losses are neglected, which limits the switching losses to the stored electric charge in the output capacitance during the switching transition [3]. One should note that the NPT configuration has been chosen as a first order design but does not reflect an optimal design for both diamond [20] and SiC devices [37,38].…”

“…At high junction temperatures (e.g. higher than 400K), such devices exhibit a high free hole concentration thanks to better dopant ionization, which, combine to the high free carrier mobility, makes these devices attractive in the context of power electronics [25].…”

Inversion-type p-channel diamond MOSFET issues

“…Recently, Kawarada's group reported the first vertical H-diamond MOS-FETs [24,25]. In addition, Pernot's group proposed the deep depletion concept and concentrated on the oxygen-terminated diamond (O-diamond) MOSFETs [26][27][28]. However, both Hand O-diamond MOSFETs basically demonstrate normally on characteristics.…”