1999
DOI: 10.1016/s0924-4247(98)00326-4
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Recent advances in silicon etching for MEMS using the ASE™ process

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Cited by 165 publications
(105 citation statements)
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“…A 3-m-thick layer of resist was deposited, patterned into a staircase layout by contact lithography, and hard-baked to act as a surface mask. The silicon was then etched to 100 m depth in an inductively coupled plasma etcher using a cyclic etch-passivation process (see, e.g., [9]). After etching, residual resist was stripped in a plasma asher.…”
mentioning
confidence: 99%
“…A 3-m-thick layer of resist was deposited, patterned into a staircase layout by contact lithography, and hard-baked to act as a surface mask. The silicon was then etched to 100 m depth in an inductively coupled plasma etcher using a cyclic etch-passivation process (see, e.g., [9]). After etching, residual resist was stripped in a plasma asher.…”
mentioning
confidence: 99%
“…Using wafers of 100 mm diameter, each wafer yields sufficient dies A hard mask layer consisting of a thick layer of Shipley AZ9260 photoresist is first deposited on the substrate side, and patterned with the outer layer features (Mask #1). This pattern is transferred through the substrate to the oxide interlayer (Step 2), using a Surface Technology Systems Single-chamber Multiplex inductively coupled plasma (ICP) etcher, operating a variant of the cyclic etch-passivate process based on and developed by Robert Bosch GmbH [31], [33]. The etch selectivity is .…”
Section: Fabrication Of Prototypesmentioning
confidence: 99%
“…The best performance is obtained on insulating substrates [10]. However, modest performance can be obtained on intrinsic silicon, allowing low-cost structuring by deep reactive ion etching (DRIE), a method of near vertical etching which operates by a cyclic repetition of etching and passivation processes [11]. DRIE has a high rate (> 2 µm/min), and may etch through a 500 µm thick wafer in under 4 hours.…”
Section: Related Contentmentioning
confidence: 99%