High density plasmas are beginning to dominate the market for advanced anisotropic silicon etching for MEMS applications. This paper looks at the reasons behind this dominance for high etch rate, deep anisotropic etching. A discussion of anisotropic etch mechanisms highlights the need for sidewall passivation to meet these requirements. Results are presented of a novel room temperature advanced silicon etch process : 2 p.m/mm; selectivity to resist (and 1 50:1 to oxide); up to 30: 1 aspect ratio; 500 im depth capability; using a non-toxic non-corrosive environmentally acceptable fluorine based chemistry.
In the ongoing enhancement of MEMS applications, the STS Advanced Silicon Etch, (ASETM). process satisfies the demanding requirements of the industry. Typically, highly anisotropic. high aspect ratios profiles with fine CD (critical dimension) control are required. Selectivities to photoresist of 150:1 with Si etch rates of up to 10μm/min are demonstrated. Applications range from shallow etched optical devices to through wafer membrane etches. This paper details some of the fundamental trends of the ASETM process and goes on to discuss how the process has been enhanced to meet product specifications. Parameter ramping is a powerful technique used to achieve the often-conflicting requirements of high etch rate with good profile/CD control. The results are presented in this paper.
Increasing the luminance of white LEDs to the 200 Mnit level and beyond, opens a completely new design space for a wide range of lighting applications, by allowing significant reductions in optics and luminaire size as well as costs. Moreover, new applications, such as dynamic beam steering, are enabled by the ability to create arrays of densely packed, individually addressable high‐luminance emitters. The development of such high‐luminance LEDs requires improvements in all LED technology elements. In this paper, we discuss recent advances in epitaxy, die, phosphor, and package technology that are critical to achieving these benefits.
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