Realizing Electronic Synapses by Defect Engineering in Polycrystalline Two-Dimensional MoS₂ for Neuromorphic Computing

Abstract

Neuromorphic computing based on two-dimensional transition-metal dichalcogenides (2D TMDs) has attracted significant attention recently due to their extraordinary properties generated by the atomic-thick layered structure. This study presents sulfur-defect-assisted MoS2 artificial synaptic devices fabricated by a simple sputtering process, followed by a precise sulfur (S) vacancy-engineering process. While the as-sputtered MoS2 film does not show synaptic behavior, the S vacancy-controlled MoS2 film exhibits excellent synapse with remarkable nonvolatile memory characteristics such as a high switching ratio (∼103), a large memory window, and long retention time (∼104 s) in addition to synaptic functions such as paired-pulse facilitation (PPF) and long-term potentiation (LTP)/depression (LTD). The synaptic device working mechanism of Schottky barrier height modulation by redistributing S vacancies was systemically analyzed by electrical, physical, and microscopy characterizations. The presented MoS2 synaptic device, based on the precise defect engineering of sputtered MoS2, is a facile, low-cost, complementary metal-oxide semiconductor (CMOS)-compatible, and scalable method and provides a procedural guideline for the design of practical 2D TMD-based neuromorphic computing.

Solution-Processed Robust Multifunctional Memristor of 2D Layered Material Thin Film

“…Interestingly, our 2D MoS 2 memristor device depicts an attractively fast operation speed with significantly low energy consumption for the basic operations of read (R), write (W), and erase (E) as depicted in Table . Calculations show that the energy required for W, E, and R steps are about 33 pJ, 10 pJ, and 67.6 fJ, respectively, which are much lower than or comparable to those of the CMOS memory in computers and similar devices. , …”

“…Calculations show that the energy required for W, E, and R steps are about 33 pJ, 10 pJ, and 67.6 fJ, respectively, which are much lower than or comparable to those of the CMOS memory in computers and similar devices. 35,36 Further, we have performed various control experiments to confirm robustness of the resistive switching (RS) property of our 2D MoS 2 thin film memristor device. First, we did testing for an ITO/EGaIn-only device with an EGaIn drop diameter of about 500 μm (see Figure S5a in the Supporting Information) by recording I−V characteristics in multiple loops (see Figure S5b in the Supporting Information), and it shows a purely Ohmic nature, confirming metallic behavior.…”

Chalcogen Vacancy Engineering of Two-Dimensional Transition Metal Dichalcogenides for Electronic Applications

“…124,125 When a signal is transmitted from a presynaptic terminal, the receptor in a postsynaptic dendrite activates the postsynaptic neuron and subsequently delivers the chemical signal in the form of an electrical signal (Figure 7a). 126 A signal transmitted in this manner changes the synaptic weight, which refers to the connection strength between the neurons, thus inducing a change in plasticity that corresponds to potentiation or depression. Similarly, in neuromorphic devices, the conductance states or synaptic weight can be adjusted by modulating timing, voltage, and rate of electrical pulses, which emulate the critical functions of actual natural networks such as long-term potentiation (LTP), short-term potentiation (STP), long-term depression (inhibition) (LTD), and shortterm depression (inhibition) (STD).…”

Enhanced Synaptic Characteristics under Applied Magnetic Field in V2O5/NiMnIn-Based Switching Device for Neuromorphic Computing

“…The Internet of Things and machine learning generate massive electronic data workloads in the rapidly growing field of information technology. − Developing highly efficient, large data storage capacity and fast memory devices in a compact size can resolve the aforementioned issues. The performance and durability of memory devices are frequently compromised by heating effects resulting from downscaling the transistor size. − Moreover, conventional circuits fail with a reduced transistor size below 2–3 nm beyond the quantum tunneling phenomenon. − The increased data size leads to challenges for traditional computers based on von Neumann’s architecture (consisting of physical separation between processor and memory units) by slowing down their performance and consuming high power. ,− As a result, new computer designs and materials are being thoroughly investigated to potentially replace existing data storage systems.…”