Realization of a programmable rank-order filter architecture using capacitive threshold logic gates

Hatirnaz, I.; Gürkaynak, Frank K.; Leblebici, Yusuf

doi:10.1109/iscas.1999.777904

Cited by 14 publications

(3 citation statements)

References 7 publications

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“…5 shows the architecture of the order processor, which deals with sorting operations for image processing. The sorting procedure [9], [10] is implemented by a set of recon gurable hardware, which contains 8-stage processing elements for bitwise operation and a set of multiplexers to compute the rank order of a set of parallel pixels. Each stage of processing elements contains 256 parallel bit logic modules, an adder tree with 9 layers, and a comparator to compare the results of summation between stages.…”

Section: B Order Processormentioning

confidence: 99%

Tera-scale performance image stream processor with SoC architecture for multimedia content analysis

Chen

Tang

Tsai

et al. 2009

2009 IEEE Asian Solid-State Circuits Conference

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A 1.0 TOPS image stream processor, which deals with image processing tasks for multimedia content analysis, is implemented with 2.2mm 2 area in 90nm CMOS technology. Two sub processors, linear processor and order processor, are integrated to achieve tera-scale performance. In the proposed SoC architecture, the data are transferred between processors and the high bandwidth dual memory through the local media bus, which reduces the power consumption in the AHB data access. Based on the memory architecture, the maximum input data rate of the proposed image stream processor reaches 62.5 Gpixel/s, which meets the requirements for real-time HDTV image processing.

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Section: B Order Processormentioning

confidence: 99%

Tera-scale performance image stream processor with SoC architecture for multimedia content analysis

Chen

Tang

Tsai

et al. 2009

2009 IEEE Asian Solid-State Circuits Conference

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“…The modular structure of the one-bit slice described above also allows for scalable realization of the ROFs with different window sizes and word lengths. Details of the realization of this rank ordering algorithm were presented earlier in [10] and [11].…”

Section: The Rank Ordering Algorithmmentioning

confidence: 99%

“…The overall architecture is completely scalable to accommodate a wide range of window sizes and bit-lengths, and the hardware complexity only grows linearly with both of these parameters. The proposed sorter architecture is essentially based on a fully programmable modular ROF design that was presented earlier [10], [11]. In the following, we first discuss the programmable ROF architecture that forms the basis of the sorting engine, in Section 2.…”

Section: Introductionmentioning

confidence: 99%

A compact modular architecture for the realization of high-speed binary sorting engines based on rank ordering

Hatirnaz

Gürkaynak

Leblebici

2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No

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A new modular architecture is presented for the realization of high-speed binary sorting engines, based on efficient rank ordering. Capacitive Threshold Logic (CTL) gates are utilized for the implementation of the multi-input programmable majority (voting) functions required in the architecture. The overall complexity of the proposed bitserial architecture increases linearly with the number of input vectors to be sorted (window size = m) and with the bitlength of the input vectors (word size = n), and the sorter architecture can be easily expanded to accommodate large vector sets. Detailed simulations indicate that the sorter structure can operate at sampling clock rates of up to 50 MHz, where the throughput is boosted by fine-grain pipelining. It is demonstrated that the proposed sorting engine is capable of producing a fully sorted output vector set in (m+n-1) clock cycles, i.e., in linear time.

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A Balanced Capacitive Threshold-Logic Gate

López-García

Fernández-Ramos

Gago-Bohórquez

2004

Analog Integrated Circuits and Signal Processing

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Realization of a programmable rank-order filter architecture using capacitive threshold logic gates

Cited by 14 publications

References 7 publications

Tera-scale performance image stream processor with SoC architecture for multimedia content analysis

Tera-scale performance image stream processor with SoC architecture for multimedia content analysis

A compact modular architecture for the realization of high-speed binary sorting engines based on rank ordering

A Balanced Capacitive Threshold-Logic Gate

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