A Balanced Capacitive Threshold-Logic Gate

López-García, Javier; Fernández-Ramos, José; Gago-Bohórquez, Alfonso

doi:10.1023/b:alog.0000031434.48142.a3

Cited by 14 publications

(6 citation statements)

References 13 publications

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“…In the studies of Ataie et al (2019) and Zareei et al (2021), approximate adders based on the capacitive threshold logic (CTL) method have been presented. The CTL method can realize many complex Boolean functions with a simpler structure and fewer transistors compared to traditional implementation styles (Garcia et al , 2004). However, input capacitors cause parasitic effects and also significantly increase the area.…”

Section: Previous Workmentioning

confidence: 99%

Low-power and low-energy CNFET-based approximate full adder cell for image processing applications

Mehrabani

Maleknejad

Rostami

et al. 2022

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Purpose Full adder cells are building blocks of arithmetic circuits and affect the performance of the entire digital system. The purpose of this study is to provide a low-power and high-performance full adder cell. Design/methodology/approach Approximate computing is a novel paradigm that is used to design low-power and high-performance circuits. In this paper, a novel 1-bit approximate full adder cell is presented using the combination of complementary metal-oxide-semiconductor, transmission gate and pass transistor logic styles. Findings Simulation results confirm the superiority of the proposed design in terms of power consumption and power–delay product (PDP) criteria compared to state-of-the-art circuits. Also, the proposed full adder cell is applied in an 8-bit ripple carry adder to accomplish image processing applications including image blending, motion detection and edge detection. The results confirm that the proposed cell has premier compromise and outperforms its counterparts. Originality/value The proposed cell consists of only 11 transistors and decreases the switching activity remarkably. Therefore, it is a low-power and low-PDP cell.

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Section: Previous Workmentioning

confidence: 99%

Low-power and low-energy CNFET-based approximate full adder cell for image processing applications

Mehrabani

Maleknejad

Rostami

et al. 2022

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“…As a result, it loses its usefulness in ternary logic, and the outputs of the ternary (4:2) compressor must be generated by an individual circuit. The method of threshold logic is an appropriate choice for our purpose since it implements logical functions with less complexity, fewer gates, and shorter logic depth [9,23].…”

Section: Capacitive Threshold Logicmentioning

confidence: 99%

High-Performance Ternary (4:2) Compressor Based on Capacitive Threshold Logic

Mirzaee

Reza

2017

International Journal of Electronics and Telecommunications

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Abstract-This paper presents a ternary (4:2) compressor, which is an important component in multiplication. However, the structure differs from the binary counterpart since the ternary model does not require carry signals. The method of capacitive threshold logic (CTL) is used to achieve the output signals directly. Unlike the previously presented similar structure, the entire capacitor network is divided into two parts. This segregation results in higher reliability and robustness against unwanted process, voltage, and temperature (PVT) variations. Simulations are performed by HSPICE and 32nm CNFET technology. Simulation results demonstrate about 94% higher performance in terms of power-delay product (PDP) for the new design over the previous one.

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“…Referring to Fig. 1, the conventional XOR gate, required to produce S 0 , can be implemented according to (4)- (7), where F 1 is the summation of Σ in , T 0.5 , and T 2.5 (6). T x is an inverted threshold gate with the threshold value of x.…”

Section: :2 Compressormentioning

confidence: 99%

“…They are part of a new hardware-friendly mathematical methodology, which utilises scaled sum and threshold detectors. A threshold detector or generally a threshold gate is an n-input logic gate, such that the output of the gate is defined as the following equation [7]…”

Section: Introductionmentioning

confidence: 99%

“…They are part of a new hardware‐friendly mathematical methodology, which utilises scaled sum and threshold detectors. A threshold detector or generally a threshold gate is an n ‐input logic gate, such that the output of the gate is defined as the following equation [7]

Y = ({, \begin{matrix} 1em4pt \\ 1 & if \sum_{i = 0}^{n} X_{i} > T \\ 0 & if \sum_{i = 0}^{n} X_{i} < T \end{matrix})

where X i ∈ {0,1}, i = 1, …, n is a binary input variable and Y ∈ {0, 1} is a Boolean function with the threshold value of T . The proposed arithmetic method leads to regularity as well as the simultaneous generation of one or more logic gates such as NAND, NOR, and majority function.…”

Section: Introductionmentioning

confidence: 99%

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A new approach for designing compressors with a new hardware‐friendly mathematical method for multi‐input XOR gates

Daliri

Navi

Mirzaee

et al. 2017

IET Circuits, Devices & Systems

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This study presents a new scalable mathematical approach for designing compressors with any arbitrary number of inputs using multi-input threshold gates, behaving as exclusive-OR (XOR). This study relates the theoretical concept to hardware implementation. The methodology is exploited for 3:2, 7:3, and 15:4 compressors, and then implemented by using input capacitors (or resistors) and threshold detectors. The transistor-level realisation of 3:2 and 7:3 compressors is simulated by using Synopsys HSPICE and 32 nm Carbon Nanotube Field Effect Transistors technology. The proposed methodology benefits from the parallel operation of threshold detectors. Therefore, by increasing the number of inputs, the delay parameter does not increase dramatically. The layout views are also provided in order to be able to compare area for the 3:2 compressors with both capacitor and resistor networks.

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A Balanced Capacitive Threshold-Logic Gate

Cited by 14 publications

References 13 publications

Low-power and low-energy CNFET-based approximate full adder cell for image processing applications

Low-power and low-energy CNFET-based approximate full adder cell for image processing applications

High-Performance Ternary (4:2) Compressor Based on Capacitive Threshold Logic

A new approach for designing compressors with a new hardware‐friendly mathematical method for multi‐input XOR gates

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