Realistic limits to computation. II. The technological side

Fault-tolerant multi-level logic decoder for nanoscale crossbar memory arrays

“…On the other hand nanowires obtained by stress-limited oxidation [18], by e-beam lithography [19] or by spacer technology [3] might not rival in integration density, even if the wire dimension is comparable to grown wires, the pitch is generally limited in one way or another by the technology. Recently, a novel top-down process called SNAP proved the ability of achieving a lithographyindependent pitch by using a superlattice as an imprint pattern [24].…”

“…Later on, it has been claimed that the integration of molecular switches may suffer from artifacts due to the binding between the switches and the wires [21]. In reference [3], the author improved the choice of materials and suggested a better design of the organic switch, claiming the elimination of the artifacts. The organization of the memory into smaller blocks and interfacing modules was presented in [7].…”

System-Level Design for Nano-Electronics

“…Besides interconnection and logic, CNFETs and SiNWs have been proposed as fundamental device components of crossbar arrays for information storage due to their regular structure and high density [2]. Also, the information can be stored at the crosspoints in an ideally bi-stable molecular switch, but the integration of molecular switches may suffer from artifacts due to binding between switches and wires [4]. The use of defect-aware system-level design methods to improve synthesis of nanostructures into smaller and reliable blocks, and interfacing modules has already shown the potential of multi-level design methods [7].…”

“…Finally, a major challenge of nanometric technologies is the interface between nano-and micro-scale parts [4], [5], [13]. SiNWs and CNTs can be grown from gold nanocrystals and other materials, and dispersed on the silicon substrate to guarantee addressing properties [5].…”

“…have been recently proposed as a promising alternative to assemble future high-performance digital systems with billions of transistors. Nevertheless, defect tolerance has been outlined as a key element to effectively use these technologies [10], [4]. Thus, a completely new set of methodologies to design, manufacture and fabricate nano-electronics are needed.…”