Real Time H. 264 Video Encoder Implementation on A Programmable DSP Processor for Videophone Applications

Kant, Shashi; Mithun, U.; Gupta, Pooja

doi:10.1109/icce.2006.1598326

Cited by 15 publications

(5 citation statements)

References 2 publications

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“…Different algorithmic optimizations are presented in [27][28][29][30][31][32] for the reduction of computational complexity. [27] introduces an early termination algorithm for variable block size ME in H.264 while giving a Peak Signal to Noise Ratio (PSNR: metric for video quality measurement) loss of 0.13 dB (note: a loss of 0.5 dB in PSNR results in a visual quality degradation corresponding to 10% reduced bit-rate [9]) for Foreman video sequence along with an increase of 4.6% in bit rate.…”

Section: Related Workmentioning

confidence: 99%

“…It gives a speedup of 4× at the cost of approximately 1 dB for Carphone CIF video sequence. A set of optimizations related to transform and ME is given in [29]. This constitutes avoiding transform and inverse transform calculations depending upon the SAD value, calculation of Intra Prediction for four most probable modes, and fast ME with early termination of skipped MBs.…”

Section: Related Workmentioning

confidence: 99%

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Optimizing the H.264/AVC Video Encoder Application Structure for Reconfigurable and Application-Specific Platforms

Shafique¹,

Bauer²,

Henkel³

2008

J Sign Process Syst

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The H.264/AVC video coding standard features diverse computational hot spots that need to be accelerated to cope with the significantly increased complexity compared to previous standards. In this paper, we propose an optimized application structure (i.e. the arrangement of functional components of an application determining the data flow properties) for the H.264 encoder which is suitable for application-specific and reconfigurable hardware platforms. Our proposed application structural optimization for the computational reduction of the Motion Compensated Interpolation is independent of the actual hardware platform that is used for execution. For a MIPS processor we achieve an average speedup of approximately 60× for Motion Compensated Interpolation. Our proposed application structure reduces the overhead for Reconfigurable Platforms by distributing the actual hardware requirements amongst the functional blocks. This increases the amount of available reconfigurable hardware per Special Instruction (within a functional block) which leads to a 2.84× performance improvement of the complete encoder when compared to a Benchmark Application with standard optimizations. We evaluate our application structure by means of four different hardware platforms.

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Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Optimizing the H.264/AVC Video Encoder Application Structure for Reconfigurable and Application-Specific Platforms

Shafique¹,

Bauer²,

Henkel³

2008

J Sign Process Syst

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show abstract

“…To avoid memory stalls and cache coherency issues, DMA is used for external memory access [5]. Some case are, a) compressed bit-stream that resides in the external memory is loaded in chunks into the internal RAM and HDEC memories using DMA.…”

Section: F Memory Optimizationmentioning

confidence: 99%

H.264 Main Profile video decoding implementation techniques on OMAP3430IVA

Ramachandra¹,

Satish²

2010

IEEE 10th INTERNATIONAL CONFERENCE ON SIGNAL PROCESSING PROCEEDINGS

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High resolution H.264 video contents are present over Internet and local storage devices in huge number thus pushing the need of supporting high definition H.264 video decoding in current generation hand held devices. Texas Instrument's (TI) OMAP3430 (Open Multimedia Applications Platform) is a multimedia processor which is highly used in portable devices. This paper describes the efficient implementation of H.264 Main Profile video decoder on Image and Video Accelerator (IVA) subsystem of OMAP3430 platform. Major focus of current work is on algorithmic, architectural and memory level optimizations. Proposed optimization steps help in achieving real time playback of high resolution H.264 Main Profile contents on hand held devices with high performance and low power consumption.

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“…In [18,13,9], performance consideration of DSP decoding are analyzed especially regarding cache coherency maintenance and DMA transfers. In [12], energy characterization of DSP processing is addressed in terms of memory access and DMA transfers.…”

Section: Related Workmentioning

confidence: 99%

DyPS

et al. 2014

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In addition to General Purpose Processors (GPP), Multicore SoCs equipping modern mobile devices contain specialized Digital Signal Processor designed with the aim to provide better performance and low energy consumption properties. However, the experimental measurements we have achieved revealed that system overhead, in case of DSP video decoding, causes drastic performances drop and energy efficiency as compared to the GPP decoding. This paper describes DyPS, a new approach for energy-aware processor switching (GPP or DSP) according to the video quality. We show the pertinence of our solution in the context of adaptive video decoding and describe an implementation on an embedded Linux operating system with the help of the GStreamer framework. A simple case study showed that DyPS achieves 30% energy saving while sustaining the decoding performance.

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Real Time H. 264 Video Encoder Implementation on A Programmable DSP Processor for Videophone Applications

Cited by 15 publications

References 2 publications

Optimizing the H.264/AVC Video Encoder Application Structure for Reconfigurable and Application-Specific Platforms

Optimizing the H.264/AVC Video Encoder Application Structure for Reconfigurable and Application-Specific Platforms

H.264 Main Profile video decoding implementation techniques on OMAP3430IVA

DyPS

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