H.264 Main Profile video decoding implementation techniques on OMAP3430IVA

Ramachandra, Pradeepa; Satish, M R

doi:10.1109/icosp.2010.5657208

Cited by 3 publications

(1 citation statement)

References 2 publications

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“…In [18,13,9], performance consideration of DSP decoding are analyzed especially regarding cache coherency maintenance and DMA transfers. In [12], energy characterization of DSP processing is addressed in terms of memory access and DMA transfers.…”

Section: Related Workmentioning

confidence: 99%

DyPS

et al. 2014

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In addition to General Purpose Processors (GPP), Multicore SoCs equipping modern mobile devices contain specialized Digital Signal Processor designed with the aim to provide better performance and low energy consumption properties. However, the experimental measurements we have achieved revealed that system overhead, in case of DSP video decoding, causes drastic performances drop and energy efficiency as compared to the GPP decoding. This paper describes DyPS, a new approach for energy-aware processor switching (GPP or DSP) according to the video quality. We show the pertinence of our solution in the context of adaptive video decoding and describe an implementation on an embedded Linux operating system with the help of the GStreamer framework. A simple case study showed that DyPS achieves 30% energy saving while sustaining the decoding performance.

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Section: Related Workmentioning

confidence: 99%

DyPS

et al. 2014

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GPP vs DSP: A Performance/Energy Characterization and Evaluation of Video Decoding

Benmoussa¹,

Boukhobza²,

Senn³

et al. 2013

2013 IEEE 21st International Symposium on Modelling, Analysis and Simulation of Computer and Telecommunication Systems

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Parallelism Analysis of H.264 Decoder and Realization on a Coarse-Grained Reconfigurable SoC

Gu-gang

Cao

Yang

et al. 2013

IEICE Trans. Inf. & Syst.

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SUMMARYOne of the largest challenges for coarse-grained reconfigurable arrays (CGRAs) is how to efficiently map applications. The key issues for mapping are (1) how to reduce the memory bandwidth, (2) how to exploit parallelism in algorithms and (3) how to achieve load balancing and take full advantage of the hardware potential. In this paper, we propose a novel parallelism scheme, called 'Hybrid partitioning', for mapping a H.264 high definition (HD) decoder onto REMUS-II, a CGRA systemon-chip (SoC). Combining good features of data partitioning and task partitioning, our methodology mainly consists of three levels from top to bottom: (1) hybrid task pipeline based on slice and macroblock (MB) level; (2) MB row-level data parallelism; (3) sub-MB level parallelism method. Further, on the sub-MB level, we propose a few mapping strategies such as hybrid variable block size motion compensation (Hybrid VBSMC) for MC, 2D-wave for intra 4 × 4, parallel processing order for deblocking. With our mapping strategies, we improved the algorithm's performance on REMUS-II. For example, with a luma 16 × 16 MB, the Hybrid VBSMC achieves 4 times greater performance than VBSMC and 2.2 times greater performance than fixed 4 × 4 partition approach. Finally, we achieve 1080p@33fps H.264 high-profile (HiP)@level 4.1 decoding when the working frequency of REMUS-II is 200 MHz. Compared with typical hardware platforms, we can achieve better performance, area, and flexibility. For example, our performance achieves approximately 175% improvement than that of a commercial CGRA processor XPP-III while only using 70% of its area.

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H.264 Main Profile video decoding implementation techniques on OMAP3430IVA

Cited by 3 publications

References 2 publications

DyPS

DyPS

GPP vs DSP: A Performance/Energy Characterization and Evaluation of Video Decoding

Parallelism Analysis of H.264 Decoder and Realization on a Coarse-Grained Reconfigurable SoC

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