Optimizing the H.264/AVC Video Encoder Application Structure for Reconfigurable and Application-Specific Platforms

Shafique, Muhammad; Bauer, Lars; Henkel, Jörg

doi:10.1007/s11265-008-0304-5

Cited by 22 publications

(16 citation statements)

References 35 publications

(51 reference statements)

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“…Each of these functional blocks requires different Special Instructions, hence the system reconfigures the containers accordingly. In total, 9 Special Instructions are implemented for the encoder by using combinations of 10 different accelerators [34]. The implementation of the H.264 encoder on the reconfigurable system leads to a speedup of more than 20x compared to the same system without using Special Instructions.…”

Section: A Experimental Setupmentioning

confidence: 99%

Transparent structural online test for reconfigurable systems

Abdelfattah

Bauer

Braun

et al. 2012

2012 IEEE 18th International on-Line Testing Symposium (IOLTS)

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FPGA-based reconfigurable systems allow the online adaptation to dynamically changing runtime requirements. However, the reliability of modern FPGAs is threatened by latent defects and aging effects. Hence, it is mandatory to ensure the reliable operation of the FPGA's reconfigurable fabric. This can be achieved by periodic or on-demand online testing. In this paper, a system-integrated, transparent structural online test method for runtime reconfigurable systems is proposed. The required tests are scheduled like functional workloads, and thorough optimizations of the test overhead reduce the performance impact. The proposed scheme has been implemented on a reconfigurable system. The results demonstrate that thorough testing of the reconfigurable fabric can be achieved at negligible performance impact on the application. Preprint General Copyright NoticeThis article may be used for research, teaching and private study purposes. Any substantial or systematic reproduction, re-distribution, re-selling, loan or sub-licensing, systematic supply or distribution in any form to anyone is expressly forbidden. This is the author's "personal copy" of the final, accepted version of the paper published by IEEE. Abstract-FPGA-based reconfigurable systems allow the online adaptation to dynamically changing runtime requirements. However, the reliability of modern FPGAs is threatened by latent defects and aging effects. Hence, it is mandatory to ensure the reliable operation of the FPGA's reconfigurable fabric. This can be achieved by periodic or on-demand online testing.In this paper, a system-integrated, transparent structural online test method for runtime reconfigurable systems is proposed. The required tests are scheduled like functional workloads, and thorough optimizations of the test overhead reduce the performance impact. The proposed scheme has been implemented on a reconfigurable system. The results demonstrate that thorough testing of the reconfigurable fabric can be achieved at negligible performance impact on the application.

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Section: A Experimental Setupmentioning

confidence: 99%

Transparent structural online test for reconfigurable systems

Abdelfattah

Bauer

Braun

et al. 2012

2012 IEEE 18th International on-Line Testing Symposium (IOLTS)

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“…Usually, it is only used when performance and low power consumption are essential requirements [7,14,17]. In fact, the lack of flexibility typical of hardwired processors reduces their applicability to a narrow segment of the market, where the programmability is either not required or considerably reduced.…”

Section: Vlsi Designmentioning

confidence: 99%

An Efficient Multi‐Core SIMD Implementation for H.264/AVC Encoder

2012

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The optimization process of a H.264/AVC encoder on three different architectures is presented. The architectures are multiand singlecore and SIMD instruction sets have different vector registers size. The need of code optimization is fundamental when addressing HD resolutions with real-time constraints. The encoder is subdivided in functional modules in order to better understand where the optimization is a key factor and to evaluate in details the performance improvement. Common issues in both partitioning a video encoder into parallel architectures and SIMD optimization are described, and author solutions are presented for all the architectures. Besides showing efficient video encoder implementations, one of the main purposes of this paper is to discuss how the characteristics of different architectures and different set of SIMD instructions can impact on the target application performance. Results about the achieved speedup are provided in order to compare the different implementations and evaluate the more suitable solutions for present and next generation video-coding algorithms.

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“…Additionally, they are not a contribution of this thesis, but they are developed and published by my colleague Muhammad Shafique [SBH09a]. They are used for a proof of concept of the core components of this thesis, i.e.…”

Section: Notementioning

confidence: 99%

“…Compile-time Automation: In the scope of this thesis, the Special Instructions (SIs), Molecules, and Atoms where manually created, as stated in Section 3.3 and presented in [SBH09a]. As the design methodology and tool flow for the application designer and the instruction-set architecture are related to 7.2 Future Work ASIP design, the tools and algorithms of that research domain may be adapted to create SIs for RISPP automatically.…”

Section: Future Workmentioning

confidence: 99%

RISPP: A run-time adaptive reconfigurable embedded processor

Bauer

Shafique

Henkel

2009

2009 International Conference on Field Programmable Logic and Applications

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Hiermit erkläre ich an Eides statt, dass ich die von mir vorgelegte Arbeit selbständig verfasst habe, dass ich die verwendeten Quellen, Internet-Quellen und Hilfsmittel vollständig angegeben habe und dass ich die Stellen der Arbeit -einschließlich Tabellen, Karten und Abbildungen -die anderen Werken oder dem Internet im Wortlaut oder dem Sinn nach entnommen sind, auf jeden Fall unter Angabe der Quelle als Entlehnung kenntlich gemacht habe. ____________________________________ L a r s B a u e r i AcknowledgementsI want to thank my advisor Prof. Jörg Henkel for the inspirations, discussions, and opportunities he provided and shared with me. He managed to guide and to challenge me while giving me all freedom to follow my ideas and interests. Working with him was a nice experience and it definitely had a strong influence on my independent approach to work.I also want to thank all colleagues from the Chair for Embedded Systems for the nice discussions and the good time. In the last two month before submitting my thesis, especially Thomas Ebi and Sebastian Kobbe provided consistent support by helping me managing the daily workload and by sharing their coffee machines, which I cannot appreciate enough. Additionally, it is especially due to the secretaries and technicians that we can research in a good working environment and I explicitly want to acknowledge their work during all the time.Special thanks go to my colleague and room mate Muhammad Shafique. Without him, the work would not have been what it became. The technical discussions on application-and architecture-aspects improved the quality of this work more than once. I also want to thank the Master students that I supervised in the scope of this thesis.It was a nice experience to collaborate with colleagues from the groups (in alphabetical order) of Prof. AbstractReconfigurable embedded processors are a special class of processors comprising an extended instruction set that is implemented using a reconfigurable fabric. The instruction-set extension is typically application specific, but it is not required to finalize it when designing the processor. The reconfigurable fabric (e.g. a field-programmable gate array (FPGA)) allows that the accelerators that are used to implement the instruction-set extension may be reconfigured during run time without affecting the functionality of the working processor. Therefore, the accelerators -and thus the instruction-set extension -may be adapted according to the requirements of a running application.State-of-the-art reconfigurable processors require that the application programmer (or compiler) determines during compile time 'which' reconfigurations shall be performed and 'when' they shall be performed, i.e. which accelerators shall be loaded to a particular part of the reconfigurable fabric at a certain time. The problem is that it is typically not known during compile time which applications execute at the same time (i.e. in a multi-tasking environment), demanding the reconfigurable fabric. Additionally, it is not necessa...

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Optimizing the H.264/AVC Video Encoder Application Structure for Reconfigurable and Application-Specific Platforms

Cited by 22 publications

References 35 publications

Transparent structural online test for reconfigurable systems

Transparent structural online test for reconfigurable systems

An Efficient Multi‐Core SIMD Implementation for H.264/AVC Encoder

RISPP: A run-time adaptive reconfigurable embedded processor

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