Real Silicon Using Open-Source EDA

Edwards, R. Timothy; Shalan, Mohamed; Kassem, Mohamed M.

doi:10.1109/mdat.2021.3050000

Cited by 17 publications

(9 citation statements)

References 4 publications

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“…These benchmark circuits are diffeq, gcd, Kalman, ellipf, and qsort. They were synthesized at data-path widths of byte (8-bit), half-word (16-bit) and word (32-bit) and their layouts were generated using open-source digital ASIC implementation flow OpenLane [24], [25] using sky130_fd_sc_hd standard cell library. Their performances concerning die area and total time to execute the benchmarks with their standard input test vectors were recorded.…”

Section: Performance Evaluationmentioning

confidence: 99%

Novel VLSI Architectures and Micro-Cell Libraries for Subscalar Computations

Pandey

Shrimali

2022

IEEE Access

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Parallelism is the key to enhancing the throughput of computing structures. However, it is well established that the presence of data-flow dependencies adversely impacts the exploitation of such parallelism. This paper presents a case for a new computing paradigm namely subscalar digital arithmetic which is aimed at mitigating this issue. It proposes to break up atomic data and atomic operations thereon into sub-atomic data fragments and sub-atomic partial operations. Such a break-up exposes hitherto unexploited levels of parallelism by way of allowing overlap of operations even if data-dependent. Surprisingly this enhanced exploitation of latent parallelism comes with a favorable impact on the area-power characteristics of corresponding computing structures which is contrary to common sense. The paper also proposes a novel micro cell library with logic primitives at corresponding subscalar levels. The synthesized circuits for several sequential benchmarks show an order of magnitude improvement in their area-throughput figure-of-merit (FOM).INDEX TERMS Bit-level parallelism, digital arithmetic, pipelining.

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Section: Performance Evaluationmentioning

confidence: 99%

Novel VLSI Architectures and Micro-Cell Libraries for Subscalar Computations

Pandey

Shrimali

2022

IEEE Access

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“…The main goal of The OpenROAD Project is to support the entire ASIC flow, from RTL to GDSII. Additional arrangements such as OpenLane [39,40] and the OpenROAD flow scripts [41] use a set of tools to achieve the support for the entire ASIC flow. Fig.…”

Section: Open-source Technologymentioning

confidence: 99%

AV1 Arithmetic Encoder Design on Open-Source EDA

Bitencourt

Ramos

Bampi

2022

JICS

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With the increasing demand for video transmission through the Internet, video coding has become a key technology to allow this market's growth at a reduced cost. Moreover, with the inception of higher video resolutions (e.g., 4K, 8K) and their impact on video size, new video coding standards must tackle this issue to reduce video traffic demand on the global internet infrastructure. The AV1, a recently released royalties-free video coding format created by the Alliance for Open Media (AOMedia), reaches great compression rates but cannot accomplish real-time execution on software-only implementations due to its high complexity. This paper presents and analyzes AE-AV1, a high-performance 4-stage pipelined architecture to accelerate the AV1 arithmetic encoding process (part of the entropy encoder block) and make it capable of real-time execution. For the analysis, this work aims to rely on fully open-source Electronic Design Automation (EDA) tools and Package Design Kits (PDKs).

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“…Many open EDAs are widely proposed and these EDAs enable these open-source VLSI design projects. Many open-sourced CAD tools are proposed to support system design to logic design, logic synthesis, place-and-route, test insertion, verification, and summarized as sevelral RTL-to-GDS flows [3]. However, to our knowledge, tool-chain lacks library characterizer to extract timing and power of standard cells to enable precise timing and power estimation using Static Timing Analysis (STA).…”

Section: Introductionmentioning

confidence: 99%

Libretto: An Open Cell Timing Characterizer for Open Source VLSI Design

Nishizawa

Nakura

2023

IEICE Trans. Fundamentals

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We propose an open source cell library characterizer. Recently, free and open-sourced silicon design communities are attracted by hobby designers, academies and industries. These open-sourced silicon designs are supported by free and open sourced EDAs, however, in our knowledge, tool-chain lacks cell library characterizer to use original standard cells into digital circuit design. This paper proposes an open source cell library characterizer which can generate timing models and power models of standard cell library.

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Real Silicon Using Open-Source EDA

Cited by 17 publications

References 4 publications

Novel VLSI Architectures and Micro-Cell Libraries for Subscalar Computations

Novel VLSI Architectures and Micro-Cell Libraries for Subscalar Computations

AV1 Arithmetic Encoder Design on Open-Source EDA

Libretto: An Open Cell Timing Characterizer for Open Source VLSI Design

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