Rapl

David, Howard; Gorbatov, Eugene; Hanebutte, Ulf R.; Khanna, Rahul; Le, Christian

doi:10.1145/1840845.1840883

Cited by 434 publications

(40 citation statements)

References 17 publications

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“…The first, adaptive core gating, uses clock-gating on processor cores when memory nears its thermal limit; the second, coordinated DVFS, uses DVFS to slow the cores in the same situation. David et al in [5] describe RAPL (running average power limit), in which memory power is explicitly modelled and limited by throttling. Their power model is similar to ours.…”

Section: Related Workmentioning

confidence: 99%

Memory power management via dynamic voltage/frequency scaling

David

Fallin

Gorbatov

et al. 2011

Proceedings of the 8th ACM International Conference on Autonomic Computing

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284

209

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Energy efficiency and energy-proportional computing have become a central focus in enterprise server architecture. As thermal and electrical constraints limit system power, and datacenter operators become more conscious of energy costs, energy efficiency becomes important across the whole system. There are many proposals to scale energy at the datacenter and server level. However, one significant component of server power, the memory system, remains largely unaddressed. We propose memory dynamic voltage/frequency scaling (DVFS) to address this problem, and evaluate a simple algorithm in a real system.As we show, in a typical server platform, memory consumes 19% of system power on average while running SPEC CPU2006 workloads. While increasing core counts demand more bandwidth and drive the memory frequency upward, many workloads require much less than peak bandwidth. These workloads suffer minimal performance impact when memory frequency is reduced. When frequency reduces, voltage can be reduced as well. We demonstrate a large opportunity for memory power reduction with a simple control algorithm that adjusts memory voltage and frequency based on memory bandwidth utilization.We evaluate memory DVFS in a real system, emulating reduced memory frequency by altering timing registers and using an analytical model to compute power reduction. With an average of 0.17% slowdown, we show 10.4% average (20.5% max) memory power reduction, yielding 2.4% average (5.2% max) whole-system energy improvement.

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Section: Related Workmentioning

confidence: 99%

Memory power management via dynamic voltage/frequency scaling

David

Fallin

Gorbatov

et al. 2011

Proceedings of the 8th ACM International Conference on Autonomic Computing

Self Cite

284

209

View full text Add to dashboard Cite

show abstract

“…Towards this end, it would be useful to better understand how to throttle overloaded systems in the least obstructive way, i.e., to minimise application performance degradation while enforcing power caps. Second, the use of alternative actuators (e.g., Running Average Power Limit (RAPL) that allows control the power consumption of CPU sockets and DRAM [46]) is planned to be evaluated against already established techniques for energy efficiency in data center server environments. Third, the power-performance tradeoffs of innovative approaches increasing the performance predictability [47,48] or reliability [49,50] of cloud computing systems should be assessed to understand at what cost the proposed improvements come.…”

Section: Discussionmentioning

confidence: 99%

Power-performance tradeoffs in data center servers: DVFS, CPU pinning, horizontal, and vertical scaling

Krzywda

Ali-Eldin

Carlson

et al. 2018

Future Generation Computer Systems

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Dynamic Voltage and Frequency Scaling (DVFS), CPU pinning, horizontal, and vertical scaling, are four techniques that have been proposed as actuators to control the performance and energy consumption on data center servers. This work investigates the utility of these four actuators, and quantifies the power-performance tradeoffs associated with them. Using replicas of the German Wikipedia running on our local testbed, we perform a set of experiments to quantify the influence of DVFS, vertical and horizontal scaling, and CPU pinning on end-to-end response time (average and tail), throughput, and power consumption with different workloads. Results of the experiments show that DVFS rarely reduces the power consumption of underloaded servers by more than 5%, but it can be used to limit the maximal power consumption of a saturated server by up to 20% (at a cost of performance degradation). CPU pinning reduces the power consumption of underloaded server (by up to 7%) at the cost of performance degradation, which can be limited by choosing an appropriate CPU pinning scheme. Horizontal and vertical scaling improves both the average and tail response time, but the improvement is not proportional to the amount of resources added. The load balancing strategy has a big impact on the tail response time of horizontally scaled applications.

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“…In this section, we discuss the energy consumption of the NPB applications on the Xeon2 system. We measure the processor energy and DRAM energy by using the Running Average Power Limit (RAPL) hardware counters [11]. As shown in the performance monitoring results, the process mapping methods have a significant impact on the cache misses, the interconnect traffic, and queuing delay in memory controllers.…”

Section: Energy Consumption Evaluationmentioning

confidence: 99%

Online MPI Process Mapping for Coordinating Locality and Memory Congestion on NUMA Systems

Agung

Amrizal

Egawa

et al. 2020

JSFI

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Mapping MPI processes to processor cores, called process mapping, is crucial to achieving the scalable performance on multi-core processors. By analyzing the communication behavior among MPI processes, process mapping can improve the communication locality, and thus reduce the overall communication cost. However, on modern non-uniform memory access (NUMA) systems, the memory congestion problem could degrade performance more severely than the locality problem because heavy congestion on shared caches and memory controllers could cause long latencies. Most of the existing work focus only on improving the locality or rely on offline profiling to analyze the communication behavior. We propose a process mapping method that dynamically performs the process mapping for adapting to communication behaviors while coordinating the locality and memory congestion. Our method works online during the execution of an MPI application. It does not require modifications to the application, previous knowledge of the communication behavior, or changes to the hardware and operating system. Experimental results show that our method can achieve performance and energy efficiency close to the best static mapping method with low overhead to the application execution. In experiments with the NAS parallel benchmarks on a NUMA system, the performance and total energy improvements are up to 34% (18.5% on average) and 28.9% (13.6% on average), respectively. In experiments with two GROMACS applications on a larger NUMA system, the average improvements in performance and total energy consumption are 21.6% and 12.6%, respectively.

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Rapl

Cited by 434 publications

References 17 publications

Memory power management via dynamic voltage/frequency scaling

Memory power management via dynamic voltage/frequency scaling

Power-performance tradeoffs in data center servers: DVFS, CPU pinning, horizontal, and vertical scaling

Online MPI Process Mapping for Coordinating Locality and Memory Congestion on NUMA Systems

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