Power-performance tradeoffs in data center servers: DVFS, CPU pinning, horizontal, and vertical scaling

Abstract

Dynamic Voltage and Frequency Scaling (DVFS), CPU pinning, horizontal, and vertical scaling, are four techniques that have been proposed as actuators to control the performance and energy consumption on data center servers. This work investigates the utility of these four actuators, and quantifies the power-performance tradeoffs associated with them. Using replicas of the German Wikipedia running on our local testbed, we perform a set of experiments to quantify the influence of DVFS, vertical and horizontal scaling, and CPU pinning on end-to-end response time (average and tail), throughput, and power consumption with different workloads. Results of the experiments show that DVFS rarely reduces the power consumption of underloaded servers by more than 5%, but it can be used to limit the maximal power consumption of a saturated server by up to 20% (at a cost of performance degradation). CPU pinning reduces the power consumption of underloaded server (by up to 7%) at the cost of performance degradation, which can be limited by choosing an appropriate CPU pinning scheme. Horizontal and vertical scaling improves both the average and tail response time, but the improvement is not proportional to the amount of resources added. The load balancing strategy has a big impact on the tail response time of horizontally scaled applications.

Energy-aware Task Scheduling Strategies for Multi-core Embeddded Systems

“…The application of DVFS and DPM lowpower technology further reduces the energy consumption of heterogeneous multi-core embedded systems [6], [13]. The DVFS technology provides several discrete voltage levels, and the processor can independently and dynamically adjust its own voltage supply to save energy [14], [15], [16]. DPM technology allows the idling processors to enter sleep mode to reduce power consumption [17].…”

Dynamic CPU frequency scaling using machine learning for NFV applications.

“…It can be either chipwide, in which all cores are scaled at the same frequency, and per-core, in which each core can operate at different frequencies (KUANG; BHUYAN; KLEFSTA, 2012). The DVFS framework is well accepted as an approach to decrease the processors energy consumption, since it enables modifying the performance and energy capabilities by scaling the CPU voltage and frequency (KRZYWDA et al, 2018;SUEUR;HEISER, 2010). The CPU clock is coupled with a determined voltage level so that frequency scaling leads to simultaneous variation of the voltage values.…”

“…ZOMAYA, 2011). Furthermore, it is coarse grained, presenting few possible settings, as a limited number of frequencies can be selected (KRZYWDA et al, 2018).…”

“…Thus, several approaches that aim at enhancing resource manage to achieve better energy efficiency have been proposed in the literature. These approaches can be divided into two categories according to Krzywda et al (2018), server consolidation and server throttling, as described in Figure 7. Section 3.2.1 and Section 3.2.2 explain briefly each category and provide solutions found in the literature that can be related to NFV applications.…”

“…powers them down almost completely. Krzywda et al (2018) evaluated the approaches of speed scaling and CPU pinning to understand the power consumption reduction and also the performance degradation. As expected, the average response time worsens when techniques to improve energy efficiency in servers are employed.…”