Rapid IP Design of Variable-length Cached-FFT Processor for OFDM-based Communication Systems

Lee, Yu-Hung; Yu, Tzu-Hao; Huang, Kuo-Ken; Wu, An-Yeu

doi:10.1109/sips.2006.352556

Cited by 10 publications

(2 citation statements)

References 8 publications

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“…Here we prove our discussion in Section 3, the pipeline architecture have a higher throughput but loss on power efficiency. The authors of [5,18,19] proposed memory based Application-Specific Integrated Circuit (ASIC) for scalable DFT engine. The proposed engine in [5] enables runtime configuration of the DFT length, where the supported lengths vary only from 16-points to 4096. while the proposed engine in [18] enables reconfigurable FFT Processor, the FFT lengths vary only from 128-points to 8192. and [19] can perform 64 2048-point FFT.…”

Section: Discussionmentioning

confidence: 99%

Implementation of a reconfigurable ASIP for high throughput low power DFT/DCT/FIR engine

2012

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In this article we present an ASIP design for a discrete fourier transform (DFT)/discrete cosine transform (DCT)/finite impulse response filters (FIR) engine. The engine is intended for use in an accelerator-chain implementation of wireless communication systems. The engine offers a very high degree of flexibility, accepting and accelerating performance approaches that of any-number DFT and inverse discrete fourier transform, one and two dimension DCT, and even general implementations of FIR equations. Performance approaches that of dedicated implementations of such algorithms. A customized yet flexible redundant memory map allows processor-like access while maintaining the pipeline full in a dedicated architecture-like manner. The engine is supported by a proprietary software tool that automatically sets the rounding pattern for the accelerator rounder to maintain a required signal to quantization noise or output RMS for any given algorithm. Programming of the processor is done through a mid-level language that combines register-specific instructions with DFT/DCT/FIR specificinstructions. Overall the engine allows users to program a very wide range of applications with software-like ease, while delivering performance very close to hardware. This puts the engine in an excellent spot in the current wireless communications environment with its profusion of multi-mode and emerging standards.

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Section: Discussionmentioning

confidence: 99%

Implementation of a reconfigurable ASIP for high throughput low power DFT/DCT/FIR engine

2012

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“…According to IEEE 802.11n and 802.16e, 64-point up to 2048-point FFTs are used for different data rates. Previously, various FFT architectures and algorithms have been developed, such as a radix-2 bit-reversed algorithm with a memory-based structure [12], radix-n algorithms with a pipeline structure [13], a cached-FFT architecture [14], etc.…”

Section: Fft Optimizationmentioning

confidence: 99%

Implementations of FFT and STBD for MIMO-OFDM on a Reconfigurable Baseband Platform

Zhao

Zhou

et al. 2010

IEICE Trans. Inf. & Syst.

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SUMMARYMIMO-OFDM systems aim to improve transmission quality and/or throughput but require significant signal processing capability and flexibility at reasonable cost. This paper proposes a reconfigurable architecture and associated algorithm optimizations for these types of systems based on the IEEE 802.11n and IEEE 802.16e standards. In particular, we describe the implementation of two key computations onto this architecture, namely Fast Fourier Transform (FFT) and Space-Time Block Decoding (STBD). The design is post-layout using a UMC 0.18 micron technology at a clock rate of 100 MHz. Performance comparisons with other optimization methods and hardware implementations are given.

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Configurable FFT Processor Using Dynamically Reconfigurable Resource Arrays

Shami

Tajammul

Hemani

2018

J Sign Process Syst

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Rapid IP Design of Variable-length Cached-FFT Processor for OFDM-based Communication Systems

Cited by 10 publications

References 8 publications

Implementation of a reconfigurable ASIP for high throughput low power DFT/DCT/FIR engine

Implementation of a reconfigurable ASIP for high throughput low power DFT/DCT/FIR engine

Implementations of FFT and STBD for MIMO-OFDM on a Reconfigurable Baseband Platform

Configurable FFT Processor Using Dynamically Reconfigurable Resource Arrays

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