Future biomedical and internet-of-things applications are driving the volume of wireless sensors into the cubic-mm regime. At the mm-scale, complete integration is necessary, and operation within the limits of a micro-battery becomes a primary challenge [1]. With CMOS scaling and ultra-low-power circuits reducing battery volume, the antenna and crystal quickly become the largest components in a cubic-mm node. Higher-frequency operation and silicon-based timing circuits are critical to integrate these components. This paper presents a fully-integrated 9.8GHz impulse-radio ultra-wideband (IR-UWB) radio with an on-chip 2mm monopole and the option of wire-bonding to an off-chip antenna. The crystal is replaced with a novel temperature-compensated relaxation oscillator. Due to modern mm-scale battery limitations, the peak current draw must be <100μA [2], far below typical radio power consumption. Furthermore, external capacitors are too large for mm-scale nodes; thus, duty-cycling only at the packet level is not an option. This IR-UWB radio includes current-limiting at the battery supply, and the integrated modem duty-cycles the RF front-end at the bit-level in order to operate from integrated storage capacitance. Finally, many recent transceivers operate at <1V [3,4]; however the voltage of a micro-battery is 3.2~4.1V [2] and integrated conversion efficiency is <80% [1,5]. Thus, this radio is designed to operate the RF blocks over the entire battery voltage range.The architecture for the IR-UWB radio is shown in Fig. 25.2.1. The transmitter (TX) and receiver (RX) operate at the battery voltage, through a current limiter (CL) to protect the micro-battery from over-current and under-voltage. An internal storage capacitor allows higher current draws from the TX and RX during duty-cycled operation. Digital baseband blocks operate from a 1.2V V DD to reduce power consumption. To survive on the limited resources of the microbattery, all blocks on the radio have a low-power sleep state. RF and other analog blocks are duty-cycled at the bit level by the baseband controller, while baseband blocks are duty-cycled at the packet level by a separate sleep controller. The sleep controller remains on continuously unless an under-voltage condition occurs. The sleep controller begins and ends the wake-up procedure for each packet via I2C communication with modified I/Os to eliminate pull-up resistors. The I2C controller provides bidirectional communication with other stacked die in a sensor node.The receiver uses the non-coherent, energy-detection architecture shown in Fig. 25.2.2. Four RF gain stages amplify the 9.8GHz UWB pulses before downconverting with a squaring mixer. The signal then passes through a baseband gain stage before the signal path is split. Along one path, the pulses are passed directly to a comparator. The other path lowpass filters (LPFs) the signal to provide an auto-zeroed, DC-compensated reference level for comparison. A reset signal enables fast settling of the LPF for fast RX turn-on. Finally, a continuous-...
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