Random and systematic defect analysis using IDDQ signature analysis for understanding fails and guiding test decisions

Nigh, P.; Gattiker, A.

doi:10.1109/test.2004.1386966

Cited by 25 publications

(7 citation statements)

References 35 publications

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“…4a illustrates the time behaviour of the I DDQ (with normalised current units) for two different patterns of the defective device. Similar timedependent I DDQ behaviour has been previously observed [6]. The two considered patterns activate the defect and set the faulty net to a logic value opposite to that of the defect-free case.…”

Section: Full Open Defect Modelsupporting

confidence: 78%

Impact of gate tunnelling leakage on CMOS circuits with full open defects

et al. 2007

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Electronics Letter of the MonthInterconnecting lines with full open defects become floating lines. In nanometric CMOS technologies, gate tunnelling leakage currents impact the behaviour of these lines, which cannot be considered\ud electrically isolated anymore. The voltage of the floating node is determined by its neighbours and leakage currents. After some time an equilibrium is reached between these effects. Theoretical analysis and experimental evidence of this behaviour are presented.Peer ReviewedAward-winningPostprint (published version

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Section: Full Open Defect Modelsupporting

confidence: 78%

Impact of gate tunnelling leakage on CMOS circuits with full open defects

et al. 2007

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“…The information contained in current signatures [12], [19]- [20] can facilitate defect diagnosis, and specially, the diagnosis of bridging defects. A real example is illustrated in Fig.…”

Section: Current Signatures Of Bridging Defectsmentioning

confidence: 99%

Diagnosis of Bridging Defects Based on Current Signatures at Low Power Supply Voltages

Arumí

Rodríguez-Montañés

Figueras

et al. 2007

25th IEEE VLSI Test Symposium (VTS'07)

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Improvement of diagnosis methodologies is a key factor for fast failure analysis and yield improvement. As bridging defects are a common defect type in CMOS circuits, diagnosing this class of defect becomes relevant for present and future technologies. Bridging defects cause two additional current components, the bridge and the downstream current. This work presents the effect of the downstream current on current signatures and its impact on the diagnosis of such defects. We demonstrate that the impact of downstream current is minimized at low power supply (V DD ) values. Therefore, current measurements at low power supply voltages are proposed to enhance bridge diagnosis. Experimental evidence of this behaviour is presented for real devices. Furthermore, current signatures measured at V VLV are used for the diagnosis of fifteen failing 0.18µm technology devices, which are demonstrated to contain a bridging defect.

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“…In [6] and [7] all measurements are compared collectively as a current signature, analogous to the delay-test signature used in [4], which was found to be more robust than individual comparisons. A different data representation is used in [8], where the author proposes detecting outliers using current ratios between a samples minimum and maximum measurement.…”

Section: Related Workmentioning

confidence: 99%

Minimizing outlier delay test cost in the presence of systematic variability

Drmanac

Bolin

Wang

et al. 2009

2009 International Test Conference

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This work proposes a methodology to minimize the application cost of outlier analysis when applied to delay testing in the presence of systematic variability. Support vector machine (SVM) outlier analysis algorithms and traditional entropy measures are used to detect delay defects by choosing a minimum number of suitable test clocks. Monte Carlo simulations generate realistic test data while information content measurements guide test clock selection. Exhaustive simulation found tradeoffs between reducing the number of clocks, patterns, and chip samples. Substantial cost reduction was obtained with proper clock selection, while minimizing both test patterns and circuit samples required for effective outlier analysis.

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Random and systematic defect analysis using IDDQ signature analysis for understanding fails and guiding test decisions

Cited by 25 publications

References 35 publications

Impact of gate tunnelling leakage on CMOS circuits with full open defects

Impact of gate tunnelling leakage on CMOS circuits with full open defects

Diagnosis of Bridging Defects Based on Current Signatures at Low Power Supply Voltages

Minimizing outlier delay test cost in the presence of systematic variability

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