Diagnosis of Bridging Defects Based on Current Signatures at Low Power Supply Voltages

Arumí, D.; Rodríguez-Montañés, R.; Figueras, Joan; Eichenberger, S.; Hora, C.; Kruseman, B.; Lousberg, M.; Maihi, A.K.

doi:10.1109/vts.2007.27

Cited by 8 publications

(9 citation statements)

References 26 publications

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“…It was further investigated by analyzing the detailed diagnosis callout, which shows that majority of test cases diagnosed exactly at 1.2V are included in the CNT group with 2-3 candidate bridges at other voltage setting. From this experiment we can observe that the lowest voltage setting achieves highest diagnosis accuracy for a large majority of circuits, which is similar to the findings reported recently by Arumi et al, using current based diagnosis [23].…”

Section: A First Experimentssupporting

confidence: 90%

Diagnosis of Multiple-Voltage Design With Bridge Defect

Khursheed

Al-Hashimi

Reddy

et al. 2009

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-Multiple-voltage is an effective dynamic power reduction design technique, commonly used in low power ICs. To the best of our knowledge there is no reported work for diagnosing multiple-voltage enabled ICs and the aim of this paper is to propose a method for diagnosing bridge defects in such ICs. Using synthesized ISCAS benchmarks, with realistic extracted bridges and a parametric fault model, the paper investigates the impact of varying supply voltage on the accuracy of diagnosis and demonstrates how the additional voltage settings can be leveraged to improve the diagnosis resolution through a novel multi-voltage diagnosis algorithm. In addition it also identifies the most useful voltage settings to reduce diagnosis cost by eliminating tests at certain voltage setting using the proposed multi-voltage diagnosis approach thereby achieving high diagnosis accuracy at reduced cost.

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Section: A First Experimentssupporting

confidence: 90%

Diagnosis of Multiple-Voltage Design With Bridge Defect

Khursheed

Al-Hashimi

Reddy

et al. 2009

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…This prior work motivated us to consider using multiple voltage levels for pre-bond TSV test. Since multiple-voltage testing neither imposes limits on the test equipment nor requires extra on-chip DfT structures, it can be applied in practice without introducing additional hardware costs [26], [27]. Since pre-bond TSV test does not require long test sequences (scan data), test time does not grow significantly if multiple voltages are used.…”

Section: Related Prior Workmentioning

confidence: 99%

Contactless pre-bond TSV fault diagnosis using duty-cycle detectors and ring oscillators

Deutsch

Chakrabarty

2015

2015 IEEE International Test Conference (ITC)

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Defects in TSVs due to fabrication steps decrease the yield and reliability of 3D stacked ICs, hence these defects need to be screened early in the manufacturing flow. We propose a noninvasive method for pre-bond TSV test and diagnosis that does not require TSV probing. We use open TSVs as capacitive loads of their driving gates and measure the propagation delay by means of ring oscillators. Defects in TSVs cause variations in their RC parameters and therefore lead to variations in the propagation delay. By measuring these variations, we can detect resistive open and leakage faults. In addition, we use duty-cycle detectors to measure the duty cycle of the oscillation signal. These measurements provide additional information for fault analysis and hence increase the diagnosis accuracy. We exploit different voltage levels to increase the sensitivity of the test and its robustness against random process variations. We also present a method to create a regression model based on artificial neural networks to predict the fault size. As input, this model uses both the oscillation period and the duty cycle measured at multiple different voltage levels. The model classifies the type of the fault and predicts its size. Moreover, the regression model can effectively determine whether a TSV has both leakage and resistive-open defects. Results on fault-diagnosis effectiveness are presented through HSPICE simulations using realistic models for a 45nm CMOS technology. The estimated DfT area cost of our method is negligible for dies of realistic size.

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“…This prior work motivated us to consider using multiple voltage levels for pre-bond TSV test. Since multiple-voltage testing neither imposes limits on the test equipment nor requires extra on-chip DfT structures, it can be applied in practice without introducing additional hardware costs [58,59]. Since pre-bond TSV test does not require long test sequences (scan data), test time does not grow significantly if multiple voltages are used.…”

Section: Huang Et Al Have Developed a Solution For Detecting Resistimentioning

confidence: 99%

Test and debug solutions for 3D-stacked integrated circuits

Deutsch

Chakrabarty

2015

2015 IEEE International Test Conference (ITC)

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Three-dimensional (3D) stacking using through-silicon vias (TSVs) promises higher integration levels in a single package, keeping pace with Moore's law. TSVs are small copper or tungsten vias that go vertically through the substrate of a die and provide vertical interconnects to a die stacked on top. TSV-based interconnects have benefits in terms of performance, interconnect density, and power efficiency.Testing has been identified as a showstopper for volume manufacturing of 3D-stacked integrated circuits (3D ICs). A number of challenges associated with 3D test need to be addressed before 3D ICs can become economically viable. This dissertation provides solutions to new challenges related to 3D test content, test access, diagnosis and debug.Test content specific to 3D ICs targets defect that occur during TSV manufacturing and stacking process. One example is the effect of thermo-mechanical stress due to TSV fabrication process on the surrounding logic gates. In this dissertation, we analyze these effects and their consequences for delay testing. We provide quantitative results showing that the use of TSV-stress oblivious circuit models for test generation leads to considerable reduction in delay-test quality. We propose a test flow that uses TSV-stress aware circuit models to improve test quality.Another example of 3D-specific test challenge is the testability of TSVs. In this dissertation, we focus on TSV test prior to die bonding, as access to TSVs is limited at this stage. We propose a non-invasive method for pre-bond TSV test that does iv not require TSV probing. The method uses ring oscillators and duty-cycle detectors in order to detect variations in propagation delay of gates connected to a single-sided TSV. Based on the measured variations, we can diagnose the TSV and predict the size of resistive-open and leakage faults using a regression model based on artificial neural networks. In addition, we exploit different voltage levels to increase the robustness of the test method.In order to efficiently deliver test content to structures under test in a 3D stack, 3D design-for-test (DfT) architectures are needed. In this dissertation, we discuss existing 3D-DfT architectures and their optimization. We propose an optimization approach that takes uncertainties in input parameters into account and provides a solution that is efficient in the presence of input-parameter variations and minimizes test time, therefore reducing test cost.Post-silicon debug is a major challenge due to continuously increasing design complexity. Traditional debug methods using signal tracing suffer from the limited capacity of on-chip trace buffers that only allow for signal observation during a short time window. This dissertation proposes a low-cost debug architecture for massive signal tracing in 3D-stacked ICs with wide-I/O DRAM dies. The key idea is to use available on-chip DRAM for trace-data storage, which results in a significant increase of the observation window compared to traditional methods that use trace buffers. ...

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Diagnosis of Bridging Defects Based on Current Signatures at Low Power Supply Voltages

Cited by 8 publications

References 26 publications

Diagnosis of Multiple-Voltage Design With Bridge Defect

Diagnosis of Multiple-Voltage Design With Bridge Defect

Contactless pre-bond TSV fault diagnosis using duty-cycle detectors and ring oscillators

Test and debug solutions for 3D-stacked integrated circuits

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