Minimizing outlier delay test cost in the presence of systematic variability

Proceedings of the International Conference on Computer-Aided Design

2012

Leveraging machine learning has been proven as a promising avenue for addressing many practical circuit design and verification challenges. We demonstrate a novel active learning guided machine learning approach for characterizing circuit performance. When employed under the context of support vector machines, the proposed probabilistically weighted active learning approach is able to dramatically reduce the size of the training data, leading to significant reduction of the overall training cost. The proposed active learning approach is extended to the training of asymmetric support vector machine classifiers, which is further sped up by a global acceleration scheme. We demonstrate the excellent performance of the proposed techniques using three case studies: PLL lock-time verification, SRAM yield analysis and prediction of chip peak temperature using a limited number of on-chip temperature sensors.

“…Thereforeŵ * is the normalization of the optimal separating hyperplane of SVM represented by w * and the distance between support vectors and this hyperplane is the margin m in (5).…”

Section: Version Spacementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Classifying circuit performance using active-learning guided support vector machines

Proceedings of the International Conference on Computer-Aided Design

2012

“…Machine learning has wide application in circuit testing [13]. There are three main categories: (i) outlier identification [21], (ii) test cost reduction [22, 23], (iii) feature ranking [10], and (iv) circuit performance prediction [10, 24]. In particular, machine learning considering voltage droop has been proposed in [12].…”

Section: Past Researchmentioning

confidence: 99%

PSN‐aware circuit test timing prediction using machine learning

Liu

Han

IET Computers & Digital Techniques

et al. 2017

Excessive power supply noise (PSN) such as IR drop can cause yield loss when testing very large scale integration chips. However, simulation of circuit timing with PSN is not an easy task. In this study, the authors predict circuit timing for all test patterns using three machine learning techniques, neural network (NN), support vector regression (SVR), and least-square boosting (LSBoost). To reduce the huge dimension of raw data, they propose four feature extractions: input/output transition (IOT), flip-flop transition in window (FFTW), switching activity in window (SAW), and terminal FF transition of long paths (PATH). SAW and FFTW are physical-aware features while PATH is a timing-aware feature. Their experimental results on leon3mp benchmark circuit (638 K gates, 2 K test patterns) show that, compared with the simple IOT method, SAW effectively reduced the dimension by up to 472 times, without significant impact on prediction accuracy [correlation coefficient = 0.79]. Their results show that NN has best prediction accuracy and SVR has the least under-prediction. LSBoost uses the least memory. The proposed method is more than six orders of magnitude faster than traditional circuit simulation tools.

“…Therefore,ŵ * is the normalization of the optimal separating hyperplane represented by w * , and the distance between support vectors and this hyperplane is the margin m in (5).…”

Section: (A)]mentioning

confidence: 99%

“…Voting-based methods are used in [3] and [4] to train analog performance models parameterized in design parameters. In [4] and [5], one-class SVM is adopted to represent analog circuit performance and perform outlier analysis for cost reduction of delay test. In [6] and [7], regression techniques are used to analyze circuit reliability and rank design features that contribute to unmodeled systematic timing effects.…”

Section: Introductionmentioning

confidence: 99%

Circuit Performance Classification With Active Learning Guided Sampling for Support Vector Machines

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

2015

Leveraging machine learning has been proven as a promising avenue for addressing many practical circuit design and verification challenges. We demonstrate a novel active learning guided machine learning approach for characterizing circuit performance. When employed under the context of support vector machines (SVMs), the proposed probabilistically weighted active learning approach is able to dramatically reduce the size of the training data, leading to significant reduction of the overall training cost. The proposed active learning approach is extended to the training of asymmetric SVM classifiers, which is further sped up by a global acceleration scheme. We demonstrate the excellent performance of the proposed techniques using four case studies: 1) dc/dc converter ripple noise analysis; 2) phase-locked loop lock-time verification; 3) reliability analysis of a ring oscillator with respect to process variations and initial conditions; and 4) prediction of chip peak temperature using a limited number of on-chip temperature sensors.