Raising the abstraction level of HDL for control-dominant applications

2013 IEEE 21st Annual International Symposium on Field-Programmable Custom Computing Machines

2013

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Decades of research in the field of high level hardware description now result in tools that are able to automatically transform C/C++ constructs into highly optimized parallel and pipelined architectures. Such approaches work fine when the control flow is a priory known since the computation results in a large dataflow graph that can be mapped into the available operators. Nevertheless, some applications have a control flow that is highly dependant on the data. This paper focuses on the hardware implementation of such applications and presents a high level synthesis methodology applied to a Hardware Description Language (HDL) in which assignments correspond to self-synchronized connections between predefined data streaming sources and sinks. A data transfer occurs over an established connection when both source and sink are ready, according to their synchronization interfaces. Founded on a high-level communicating FSM programming model, the language allows the user to describe and dynamically modify streaming architectures exploiting spatial and temporal parallelism. Our compiler attempts to maximize the number of transfers at each clock cycle and automatically fixes the potential combinatorial loops induced by the dynamic connection of dependant sources and sinks. The methodology is applied to the synthesis of a pipelined floating point accumulator using the Delayed-Buffering (DB) reduction method. The results we obtain are similar to state-of-the-art dedicated architectures but require much less design time and expertise.

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Section: A Hardware Description Languagementioning

confidence: 99%

High-Level Description and Synthesis of Floating-Point Accumulators on FPGA

2013 IEEE 21st Annual International Symposium on Field-Programmable Custom Computing Machines

2013

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“…The featured Synchronized-Transfer-Level (STL) methodology adds a constraint programming paradigm, allowing the specification of logical rules constraining the authorization of data transfers over different connections [14]. Conceptually, the authorization of data transfers over synchronized connections is equivalent to the firing of a transition between two places in a Petri Net.…”

Section: Introductionmentioning

confidence: 99%

Synchronized-transfer-level design methodology applied to hardware matrix multiplication

2012 International Conference on Reconfigurable Computing and FPGAs

2012

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In an effort to reduce the productivity gap separating hardware design and software programming practices, this paper presents the application of our synchronizedtransfer-level hardware design methodology to the implementation of a hardware matrix multiplication accelerator. The methodology builds on a hardware description language for which the designer manages dynamic connections between sources and sinks that may not always be ready to send or receive data tokens. In addition to these connections, the designer can constrain the authorization of data transfers by the means of logical rules that make transfers dependant on each other. Combining both finite state machine and constraint programming paradigms, the featured description language enhances the ability to express and exploit low-level parallelism. A compiler automates the generation and the optimization of the synchronization logic, whose low-level complexity is thus hidden to the designer. Applied to the design of the pipelined matrix multiplication circuit, the proposed methodology leads to similar computing performances than the dedicated designs reported in the literature but within shorter design times (a single day), simpler source code and no need for advanced hardware design skills.

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Fast description and synthesis of control-dominant circuits

Computers & Electrical Engineering

2014