Fast description and synthesis of control-dominant circuits

As modern field-programmable gate arrays (FPGA) enable high computing performance and efficiency, their programming with low-level hardware description languages is time-consuming and remains a major obstacle to their adoption. High-level synthesis compilers are able to produce register-transfer-level (RTL) designs from C/C++ algorithmic descriptions, but despite allowing significant design-time improvements, these tools are not always able to generate hardware designs that compare to handmade RTL designs. In this article, we consider synthesis from an intermediate-level (IL) language that allows the description of algorithmic state machines handling connections between streaming sources and sinks. However, the interconnection of streaming sources and sinks can lead to cyclic combinational relations, resulting in undesirable behaviors or un-synthesizable designs. We propose a functional-level methodology to automate the resolution of such cyclic relations into acyclic combinational functions. The proposed IL synthesis methodology has been applied to the design of pipelined floating-point cores. The results obtained show how the proposed IL methodology can simplify the description of pipelined architectures while enabling performances that are close to those achievable through an RTL design methodology.

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Fast description and synthesis of control-dominant circuits

Cited by 3 publications

References 20 publications

Intermediate-Level Synthesis of a Gauss-Jordan Elimination Linear Solver

Intermediate-Level Synthesis of a Gauss-Jordan Elimination Linear Solver

Design of FPGA-Based Mealy FSMs with Counters

Automated Synthesis of Streaming Transfer Level Hardware Designs

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