2012 International Conference on Reconfigurable Computing and FPGAs 2012
DOI: 10.1109/reconfig.2012.6416789
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Synchronized-transfer-level design methodology applied to hardware matrix multiplication

Abstract: In an effort to reduce the productivity gap separating hardware design and software programming practices, this paper presents the application of our synchronizedtransfer-level hardware design methodology to the implementation of a hardware matrix multiplication accelerator. The methodology builds on a hardware description language for which the designer manages dynamic connections between sources and sinks that may not always be ready to send or receive data tokens. In addition to these connections, the desig… Show more

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