2017 29th International Conference on Microelectronics (ICM) 2017
DOI: 10.1109/icm.2017.8268893
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Radix-4 successive cancellation decoding of polar codes with partial sum lookahead

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Cited by 2 publications
(1 citation statement)
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“…In the spirit of further reducing the latency, Yuan et al [98] proposed a 2-bit decoding architecture for SC decoders, which concurrently processes two bits during the last stage of the SC decoding process. Look-ahead techniques were also invoked in [98] and recently in [129], while memory-efficient hardware implementations were presented in [124], [130].…”
Section: A Successive Cancellation (Sc) Decodermentioning
confidence: 99%
“…In the spirit of further reducing the latency, Yuan et al [98] proposed a 2-bit decoding architecture for SC decoders, which concurrently processes two bits during the last stage of the SC decoding process. Look-ahead techniques were also invoked in [98] and recently in [129], while memory-efficient hardware implementations were presented in [124], [130].…”
Section: A Successive Cancellation (Sc) Decodermentioning
confidence: 99%