A simplified radix-4 successive cancellation decoder with partial sum lookahead

Hassan, Hussein G. H.; Hussien, Amr M. A.; Fahmy, H. M.

doi:10.1016/j.aeue.2018.09.027

Cited by 4 publications

(2 citation statements)

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“…As 3 compared to the decoder in [19], FFs are reduced by 34%, throughput increased by twice and RAM usage is 4 increased by 40% is realized in our decoder. The work [23] reports implementation results of the decoder up to 5 N = 2 16 . It shows an increase in LUT and FF usage by 80-84% and a reduction in RAM usage by 29% with 6 comparable throughput than the proposed decoder for the same code length.…”

Section: Hardware Analysis and Comparisonmentioning

confidence: 99%

“…However, the hardware resources such as LUT, FF, and random access memory (RAM) usage is very high compared to the other conventional decoders, which leads to usage of this decoder only for limited applications. In [16], a radix-4 SC decoder uses partial-sum look-ahead, special subcode decoding to reduce latency and drastically enhance the throughput. A low complex merged processing element was implemented in [17], in which application-specific integrated circuits (ASIC) reported notable improvement in throughput and latency.…”

Section: Introductionmentioning

confidence: 99%

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Improving utilization rate of semi-parallel successive cancellation architecture for polar codes using 2-bit decoding

2021

Turk J Elec Eng & Comp Sci

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Polar codes are the capacity-achieving error-correcting code proved to be a significant invention in coding theory. It can achieve channel capacity at infinite code length N due to its explicit code construction. However, the processing complexity along with the higher latency due to successive cancellation (SC) decoding is being a major design issue, which reduces the utilization rate in the decoder architectures. This paper presents a modified semi-parallel architecture for decoding polar code with a better decoding latency. Precomputation and look-ahead techniques are used to generate two bits in the final stage. Pipelined partial-sum unit with a less critical path reduces hardware complexity independent of code length. Hence, the proposed architecture reduces the latency by 2.7 times leads to increase in utilization rate than prior semi-parallel architecture. For a code length of N = 2 10 , the proposed architecture shows 62.7% and 94% improved utilization rate than the conventional semi-parallel architecture and 2-bit SC decoder respectively. Compared to the conventional semi-parallel decoder for N = 2 17 , hardware resource such as look-up-tables (LUT) and flip-flops (FF) usage are reduced by 98% in field programmable gate array (FPGA) leads to reduction in processing complexity. Hence, very large efficient polar decoders with a high utilization rate can be implemented in FPGA.

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Section: Hardware Analysis and Comparisonmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%