Improving utilization rate of semi-parallel successive cancellation architecture for polar codes using 2-bit decoding

Abstract

Polar codes are the capacity-achieving error-correcting code proved to be a significant invention in coding theory. It can achieve channel capacity at infinite code length N due to its explicit code construction. However, the processing complexity along with the higher latency due to successive cancellation (SC) decoding is being a major design issue, which reduces the utilization rate in the decoder architectures. This paper presents a modified semi-parallel architecture for decoding polar code with a better decoding latency. Precomputation and look-ahead techniques are used to generate two bits in the final stage. Pipelined partial-sum unit with a less critical path reduces hardware complexity independent of code length. Hence, the proposed architecture reduces the latency by 2.7 times leads to increase in utilization rate than prior semi-parallel architecture. For a code length of N = 2 10 , the proposed architecture shows 62.7% and 94% improved utilization rate than the conventional semi-parallel architecture and 2-bit SC decoder respectively. Compared to the conventional semi-parallel decoder for N = 2 17 , hardware resource such as look-up-tables (LUT) and flip-flops (FF) usage are reduced by 98% in field programmable gate array (FPGA) leads to reduction in processing complexity. Hence, very large efficient polar decoders with a high utilization rate can be implemented in FPGA.