Semi-parallel polar decoder architecture using shift-register-based partial-sum computation for 5G mobile communications

kumar, D.Dinesh; Selvakumari, R.Shantha

doi:10.1016/j.matpr.2022.04.171

Cited by 3 publications

(1 citation statement)

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“…It exhibited good error‐correcting performance than conventional SC and BP algorithms. A semiparallel architecture was implemented in [28, 29] to improve the utilization rate. Further, 2‐bit decoding techniques, such as precomputation and look‐ahead techniques were employed in [29] to improve throughput by decoding 4 bits in the last stage.…”

Section: Introductionmentioning

confidence: 99%

Fully parallel low‐density parity‐check code‐based polar decoder architecture for 5G wireless communications

Devadoss,

Ramapackiam

2023

ETRI Journal

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A hardware architecture is presented to decode (N, K) polar codes based on a low‐density parity‐check code‐like decoding method. By applying suitable pruning techniques to the dense graph of the polar code, the decoder architectures are optimized using fewer check nodes (CN) and variable nodes (VN). Pipelining is introduced in the CN and VN architectures, reducing the critical path delay. Latency is reduced further by a fully parallelized, single‐stage architecture compared with the log N stages in the conventional belief propagation (BP) decoder. The designed decoder for short‐to‐intermediate code lengths was implemented using the Virtex‐7 field‐programmable gate array (FPGA). It achieved a throughput of 2.44 Gbps, which is four times and 1.4 times higher than those of the fast‐simplified successive cancellation and combinational decoders, respectively. The proposed decoder for the (1024, 512) polar code yielded a negligible bit error rate of 10−4 at 2.7 Eb/No (dB). It converged faster than the BP decoding scheme on a dense parity‐check matrix. Moreover, the proposed decoder is also implemented using the Xilinx ultra‐scale FPGA and verified with the fifth generation new radio physical downlink control channel specification. The superior error‐correcting performance and better hardware efficiency makes our decoder a suitable alternative to the successive cancellation list decoders used in 5G wireless communication.

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Section: Introductionmentioning

confidence: 99%