Radio-Frequency Characterization of Selectively Regrown InGaAs Lateral Nanowire MOSFETs

Zota, Cezar B.; Roll, Guntrade; Wernersson, Lars‐Erik; Lind, Erik

doi:10.1109/ted.2014.2363732

Cited by 48 publications

(20 citation statements)

References 17 publications

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“…Another important aspect is that the cleaning procedure should not significantly etch hydrogen silsesquioxane (HSQ) resist, which has been successfully used as growth mask for selective area growth of lateral nanowires. [8] A significant drawback of HCl cleaning is that it etches InP (etch rate for HCl 1:1 is %4 nm s À1 ), which could compromise the adhesion of HSQ. The etch rate, however, quickly decreases with decreasing HCl concentration.…”

Section: Resultsmentioning

confidence: 99%

Optimization of Near‐Surface Quantum Well Processing

Olausson

Södergren

Borg

et al. 2021

Physica Status Solidi (a)

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Herein, an optimized process flow of near‐surface quantum well metal–oxide–semiconductor field‐effect transistors (MOSFETs) based on planar layers of metalorganic vapor‐phase epitaxy (MOVPE) grown InxGa1−xAs is presented. It is found that by an optimized pre‐growth cleaning and post‐metal anneal, the quality of the MOS structure can be greatly enhanced. This optimization is a first step toward realization of a scalable platform for topological qubits based on a well‐defined network of lateral InxGa1−xAs nanowires grown by selective area growth.

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Section: Resultsmentioning

confidence: 99%

Optimization of Near‐Surface Quantum Well Processing

Olausson

Södergren

Borg

et al. 2021

Physica Status Solidi (a)

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“…The lateral nanowire MOSFET is similar to a previous device [1]. However, it has air spacers and a line gate as shown in Fig.…”

Section: Device Fabrication and Measurementsmentioning

confidence: 95%

First InGaAs lateral nanowire MOSFET RF noise measurements and model

Ohlsson

Lindelöw

Zota

et al. 2017

2017 75th Annual Device Research Conference (DRC)

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The first radio frequency (RF) noise measurements on lateral nanowire metal-oxide-semiconductor field-effect transistors (MOSFETs) and a noise model are presented. We have characterized the RF noise and scattering parameters of an indium gallium arsenide (InGaAs) device. A fitted model yields extrapolated ft = 316 GHz current gain cutoff and fmax = 166 GHz maximum oscillation frequency. This device technology is being developed for millimeter wave circuit implementations, targeting a 94 GHz carrier frequency. The modeled intrinsic Fmin < 1dB minimum noise figure obtained promises performance at the target band, given reduction of gate parasitics. In any wireless system, noise and bandwidth limits the performance. Understanding of RF noise in nanowire MOSFET devices is thereby key for realization of future radar and communications systems

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“…We name this par ticular kind of VLS growth selective lateral nano-epitaxy (SLE). Different from the conventional selective area growth of lateral structures where the selectivity is realized by patterned hard mask (SiO 2 for example) [28][29][30] and the growth direction is normal to the substrate surface, the area selectivity in SLE is provided by the seed particles and the growth occurs in parallel with the surface. Recently, lateral growth of InAs nanowires on an HSQ mask surface has been observed in a selective area growth on a GaAs substrate [31].…”

Section: Planar Nanowire Growth By Selective Lateral Epitaxymentioning

confidence: 99%

A review of III–V planar nanowire arrays: selective lateral VLS epitaxy and 3D transistors

Zhang¹,

Miao²,

Chabak³

et al. 2017

J. Phys. D: Appl. Phys.

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Nanowires have long been regarded as a promising architecture for beyond Si CMOS logic, future III-V RF electronics, next generation optoelectronic applications, as well as heterogeneous integration. The inherent 3D structure also enables new device concepts that are otherwise not accessible with conventional technology. Nanowires grown using bottom-up epitaxial methods such as metalorganic chemical vapor deposition are free of ion-induced damage, which is especially critical for III-V because of the irreversibility of such damage, and can be scaled to dimensions smaller than lithographically defined. The challenges for nanowire based devices have been the controllability and compatibility with Si CMOS manufacturing. The discovery of parallel arrays of planar III-V nanowire growth mode provides an in-plane nanowire configuration that is perfectly compatible with existing planar processing technology for industry. The selective lateral epitaxy nature guided by the metal nanoparticles via the vapor-liquid-solid (VLS) mechanism opens up a new paradigm of crystal growth and consequently enabled in situ lateral and radial junctions. In this article, we review the planar nanowire based transistor development, particularly, planar III-As compound semiconductor based transistors enabled by this bottom-up self-assembled selective lateral VLS mechanism. We first review the characteristics and mechanism of planar nanowire growth, then focus on the growth, fabrication, and DC and RF performance of metalsemiconductor field-effect transistors, metal-oxide semiconductor field-effect transistors, and high electron mobility transistors (HEMTs), before providing our perspective on future development.

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Radio-Frequency Characterization of Selectively Regrown InGaAs Lateral Nanowire MOSFETs

Cited by 48 publications

References 17 publications

Optimization of Near‐Surface Quantum Well Processing

Optimization of Near‐Surface Quantum Well Processing

First InGaAs lateral nanowire MOSFET RF noise measurements and model

A review of III–V planar nanowire arrays: selective lateral VLS epitaxy and 3D transistors

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