Radiation Hardened by Design Subsampling Phase-Locked Loop Techniques in PD-SOI

Richards, E.W.T.; Loveless, T. D.; Kauppila, J. S.; Haeffner, T. D.; Holman, W.T.; Massengill, L.W.

doi:10.1109/tns.2020.2978167

Cited by 7 publications

(5 citation statements)

References 14 publications

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“…Recently, silicon-on-insulator (SOI) technology has become increasingly important in radiation-exposed environments such as space and military electronics due to its greater immunity to single-event effect (SEE) and suppression of the latch-up effect [ 1 , 2 , 3 ]. Furthermore, due to their strong anti-interference properties, high integration density, and fast operation speed, SOI MOSFETs have been found to be applicable to signal processing circuits, especially in radiation-exposed settings [ 4 , 5 ]. It is well known that low-frequency noise plays a substantial role in the performance of low-noise signal processing circuits [ 6 ].…”

Section: Introductionmentioning

confidence: 99%

Investigation of Anomalous Degradation Tendency of Low-Frequency Noise in Irradiated SOI-NMOSFETs

et al. 2023

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In this work, we present new evidence of the physical mechanism behind the generation of low-frequency noise with high interface-trap density by measuring the low-frequency noise magnitudes of partially depleted (PD) silicon-on-insulator (SOI) NMOSFETs as a function of irradiation dose. We measure the DC electrical characteristics of the devices at different irradiation doses and separate the threshold-voltage shifts caused by the oxide-trap charge and interface-trap charge. Moreover, the increased densities of the oxide-trap charge projected to the Si/SiO2 interface and interface-trap charge are calculated. The results of our experiment suggest that the magnitudes of low-frequency noise do not necessarily increase with the increase in border-trap density. A novel physical explanation for the low-frequency noise in SOI-NMOSFETs with high interface-trap density is proposed. We reveal that the presence of high-density interface traps after irradiation has a repressing effect on the generation of low-frequency noise. Furthermore, the exchange of some carriers between border traps and interface traps can cause a decrease in the magnitude of low-frequency noise when the interface-trap density is high.

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Section: Introductionmentioning

confidence: 99%

Investigation of Anomalous Degradation Tendency of Low-Frequency Noise in Irradiated SOI-NMOSFETs

et al. 2023

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“…Various methods for hardening PLL to single-event transient (SET) have been proposed at the module level [4][5][6]. However, there are still few studies on the system-level hardening methods.…”

Section: Introductionmentioning

confidence: 99%

A system-level method for hardening phase-locked loop to single-event effects

Liang¹,

Xu²,

Yuan³

et al. 2022

Mater. Res. Express

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To mitigate the sensitivity of the charge pump in a traditional Phase-Locked Loop(PLL), a single-event-hardened PLL architecture with a proportional and integral path is proposed. The phase margin of the PLL is kept at 58.16° due to the rational design and the output clock frequency ranges from 0.8 to 3.2 GHz. The circuit-level simulation results reveal that the sensitive volume of the hardened PLL decreases by 80% ~ 95%. The novel radiation-hardened PLL circuit was implemented in a 28 nm CMOS technology and irradiated with heavy ions with a linear energy transfer between 1.9 and 65.6 MeV•cm2/mg. The proposed radiation-hardened PLL shows one order of single-event effects hardness level higher than the conventional PLL.

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“…Previous research results have shown that the charge pump (CP) is the most sensitive part of the phase-locked loop. When the charge pump circuit is exposed to the radiation environment, the error rate generated is at least two orders of magnitude higher than in other modules [10][11][12]. Therefore, in order to improve the ability of the PLL system to suppress the SET effect, it is necessary to carry out an effective hardened design for the CP.…”

Section: Introductionmentioning

confidence: 99%

A Single-Event-Hardened Scheme of Phase-Locked Loop Microsystems for Aerospace Applications

2022

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In order to improve the ability of the phase-locked loop (PLL) microsystem applied in the aerospace environment to suppress the irradiation effect, this study presents an efficient charge pump hardened scheme by using the radiation-hardened-by-design (RHBD) technology. In this study, the sensitivity analysis of the single-event transient (SET) at different nodes of charge pump and different bombardment energies is carried out. Without changing the original structure and loop parameters, a hardened scheme of phase-locked loop to suppress the single-event effect is proposed. A digital control circuit is added between the charge pump and low-pass filter, which greatly reduces the sensitivity of the charge pump to the SET. The classical double-exponential current pulse model is used to simulate the SET effect on the unreinforced and reinforced phase-locked loops, and the reliability of the proposed reinforcement scheme is verified. The simulation results based on the SMIC 130 nm standard complementary metal–oxide–semiconductor (CMOS) process show that the peak value of the transient response fluctuation of the phase-locked loop using the proposed single-event-hardened scheme decreased by 94.2%, the lock recovery time increased by 75.3%, and the maximum phase shift decreased by 90.8%. This shows that the hardened scheme can effectively reduce the sensitivity of the PLL microsystems to the SET effects.

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Radiation Hardened by Design Subsampling Phase-Locked Loop Techniques in PD-SOI

Cited by 7 publications

References 14 publications

Investigation of Anomalous Degradation Tendency of Low-Frequency Noise in Irradiated SOI-NMOSFETs

Investigation of Anomalous Degradation Tendency of Low-Frequency Noise in Irradiated SOI-NMOSFETs

A system-level method for hardening phase-locked loop to single-event effects

A Single-Event-Hardened Scheme of Phase-Locked Loop Microsystems for Aerospace Applications

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