Radiation Hardened by Design RF Circuits Implemented in 0.13 $\mu$m CMOS Technology

Design of SET tolerant LC oscillators using distributed bias circuitry

“…The SET response in LC-tank VCOs has been studied earlier [1][2][3]. The output and the bias transistor nodes of these VCOs are found to be most sensitive to SET effects [2,3].…”

“…The output and the bias transistor nodes of these VCOs are found to be most sensitive to SET effects [2,3]. The output transistor nodes in NMOS-cross coupled VCOs can be made SET tolerant by including PMOS crosscoupled loads [3].…”

“…The output and the bias transistor nodes of these VCOs are found to be most sensitive to SET effects [2,3]. The output transistor nodes in NMOS-cross coupled VCOs can be made SET tolerant by including PMOS crosscoupled loads [3]. SET sensitivity at the output transistor nodes can be further reduced by using quadrature phase oscillators at the expense of extra power consumption [1,4].…”

Design of radiation hardened wide tuning range CMOS oscillators

“…SET effects in a voltage controlled oscillator (VCO) distort its output signal in the form of phase shift, frequency shift or amplitude shift [4,9,10,12,13]. The phase/frequency shift at the output of a VCO affects the recovery time of the phase locked loop (PLL) that uses it and can result in data loss in serial links [4].…”

“…As high impedance nodes are sensitive to SET effects, the effects can be minimized by reducing impedances at sensitive nodes. NMOS cross-coupled SVCOs can be made SET tolerant by including PMOS cross-coupled switching pair, thus providing lower impedance nodes [13]. The SET effects on bias circuit can be minimized by using decoupling resistor [9].…”