Design of radiation hardened wide tuning range CMOS oscillators

Abstract

CMOS integrated circuits are prone to hazards such as Single Event Transients (SETs) caused by radiation strikes in high energy radiation environments. For synthesis of high frequency signals for circuits used in such environments, we propose use of quadrature phase LC oscillators. In addition to providing higher tolerance to SETs, these oscillators are also able to provide wider tuning range, which is otherwise difficult to achieve for high frequencies, particularly with low phase noise LC oscillators. Further improvement in the radiation tolerance is provided by addition of parallel capacitors and series resistors in tail current path. Simulation results shown 64% reduction in worst case phase offsets caused by radiation strikes generating 100 fC charge and about 20% improvement in tuning range for 14 GHz LC oscillators.

Design of SET tolerant LC oscillators using distributed bias circuitry

“…The SET tolerance of these VCOs was simulated using SET current modeled by a double exponential current pulse [1]. The radiation strike at the reverse biased drain region of the bias transistor generates SET current, which consists of an impulse drift current followed by diffusion current.…”

“…Fig. 5 shows the injected double exponential SET current pulse (I SET ) used in the simulations for 100 fC SET charge deposition due to an alpha particle strike with the linear energy transfer (LET) of~100 MeV − cm 2 /mg [1,8]. The SET current pulse (I SET ) has the rise time of 1 ps and fall time of 20 ps, which have been chosen based on the discussions in [2,8,9].…”

“…Moreover, CMOS technology scaling has led to lower supply voltages, and thus, reduced charge oscillating in the LC-tanks of the VCOs. As a result, high frequency VCOs are more vulnerable to SETs in high energy radiation environments [1]. Hence, improving radiation tolerance to SETs for high frequency VCOs is very important.…”

“…The SET response in LC-tank VCOs has been studied earlier [1][2][3]. The output and the bias transistor nodes of these VCOs are found to be most sensitive to SET effects [2,3].…”

“…The output transistor nodes in NMOS-cross coupled VCOs can be made SET tolerant by including PMOS crosscoupled loads [3]. SET sensitivity at the output transistor nodes can be further reduced by using quadrature phase oscillators at the expense of extra power consumption [1,4]. The bias transistor nodes of these VCOs require further attention to improve SET tolerance under radiation environment.…”