R-Cache: A Highly Set-Associative In-Package Cache Using Memristive Arrays

Behnam, Payman; Chowdhury, Arjun Pal; Bojnordi, Mahdi Nazm

doi:10.1109/iccd.2018.00070

Cited by 11 publications

(4 citation statements)

References 27 publications

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“…Several works propose hardware accelerators for basecalling [63,77,78] or read mapping [54,[56][57][58]62,[65][66][67][68]71,[79][80][81][82][83]. Among these accelerators, non-volatile memory (NVM)-based processing in memory (PIM) accelerators offer high performance and efficiency since NVM-based PIM provides in-situ and highly-parallel computation support for matrix-vector mul-tiplications (MVM) [101][102][103][104][105][106][107][108][109][110][111] and string matching operations [112][113][114][115][116][117][118][119][120][121][122][123][124][125][126][127][128][129][130]…”

Section: State-of-the-art Solutionsmentioning

confidence: 99%

GenPIP: In-Memory Acceleration of Genome Analysis via Tight Integration of Basecalling and Read Mapping

Mao¹,

Alser²,

Sadrosadati³

et al. 2022

Preprint

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Nanopore sequencing is a widely-used high-throughput genome sequencing technology that can sequence long fragments of a genome into raw electrical signals at low cost. Nanopore sequencing requires two computationally-costly processing steps for accurate downstream genome analysis. The first step, basecalling, translates the raw electrical signals into nucleotide bases (i.e., A, C, G, T). The second step, read mapping, finds the correct location of a read in a reference genome. In existing genome analysis pipelines, basecalling and read mapping are executed separately. We observe in this work that such separate execution of the two most time-consuming steps inherently leads to (1) significant data movement and (2) redundant computations on the data, slowing down the genome analysis pipeline.This paper proposes GenPIP, an in-memory genome analysis accelerator that tightly integrates basecalling and read mapping. GenPIP improves the performance of the genome analysis pipeline with two key mechanisms: (1) in-memory fine-grained collaborative execution of the major genome analysis steps in parallel; (2) a new technique for early-rejection of low-quality and unmapped reads to timely stop the execution of genome analysis for such reads, reducing inefficient computation. Our experiments show that, for the execution of the genome analysis pipeline, GenPIP provides 41.6× (8.4×) speedup and 32.8× (20.8×) energy savings with negligible accuracy loss compared to the state-of-the-art software genome analysis tools executed on a state-of-the-art CPU (GPU). Compared to a design that combines state-of-the-art in-memory basecalling and read mapping accelerators, GenPIP provides 1.39× speedup and 1.37× energy savings.

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Section: State-of-the-art Solutionsmentioning

confidence: 99%

GenPIP: In-Memory Acceleration of Genome Analysis via Tight Integration of Basecalling and Read Mapping

Mao¹,

Alser²,

Sadrosadati³

et al. 2022

Preprint

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“…Therefore, it can be said that in any time frame, without considering the time limit, the maximum swap operations = (the number of cache sets*the number of ways in each cache set that are based on the WF technology). This upper bound of migrations in each time frame is determined by relations (2) and (3).…”

Section: Migration Constraintmentioning

confidence: 99%

“…The growth in the required data for complex applications and an increase in the number of cores on a single chip lead to high demands for memory capacity and bandwidth [1, 2]. To mitigate the speed gap between processor and off‐chip memory, it is indispensable to exploit large, multi‐level, on‐chip cache hierarchy [3].…”

Section: Introductionmentioning

confidence: 99%

Integer linear programming model for allocation and migration of data blocks in the STT‐RAM‐based hybrid caches

Khajekarimi

Jamshidi

Vafaei

2020

IET Computers & Digital Techniques

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Spin-transfer torque random access memory (STT-RAM) has emerged as an eminent choice for the larger on-chip caches due to high density, low static power consumption and scalability. However, this technology suffers from long latency and high energy consumption during a write operation. Hybrid caches alleviate these problems by incorporating a write-friendly memory technology such as static random access memory along with STT-RAM technology. The proper allocation of data blocks has a significant effect on both performance and energy consumption in the hybrid cache. In this study, the allocation and migration problem of data blocks in the hybrid cache is examined and then modelled using integer linear programming (ILP) formulations. The authors propose an ILP model with three different objective functions which include minimising access latency, minimising energy and minimising energy-delay product in the hybrid cache. Evaluations confirm that the proposed ILP model obtains better results in terms of energy consumption and performance compared to the existing hybrid cache architecture.

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“…The bandwidth efficient write probe and on-chip neighboring tag cache (NTC) helps to optimize DRAM cache bandwidth by removing some of the tag check accesses to DRAM. R-Cache [32] proposes an RRAM based in-package memory that eliminates the bandwidth overhead of tag checks via in-situ comparison.…”

Section: Existing In-package Cache Proposalsmentioning

confidence: 99%

ReTagger

Bojnordi

Nasrullah

2019

Proceedings of the 56th Annual Design Automation Conference 2019

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3D die-stacking has enabled energy-efficient solutions for near data processing by integrating multiple dice of high-density memory layers and processor cores within the same package. One promising approach is to employ the in-package memory as a gigascale lastlevel cache for data-intensive computing. Most existing in-package cache controllers rely on the command scheduling policies borrowed from the off-chip DRAM system. Regrettably, these control policies are not specifically tailored for in-package cache traffics, which results in a limited bandwidth efficiency. This paper proposes ReTagger, a DRAM cache controller that employs repeated tags to alleviate the cost of DRAM row buffer misses. Our simulation results on a set of ten data-intensive applications indicate an average of 20% performance improvement for the proposed controller over the state-of-the-art DRAM caches.

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R-Cache: A Highly Set-Associative In-Package Cache Using Memristive Arrays

Cited by 11 publications

References 27 publications

GenPIP: In-Memory Acceleration of Genome Analysis via Tight Integration of Basecalling and Read Mapping

GenPIP: In-Memory Acceleration of Genome Analysis via Tight Integration of Basecalling and Read Mapping

Integer linear programming model for allocation and migration of data blocks in the STT‐RAM‐based hybrid caches

ReTagger

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