Quaternary Voltage-Mode Logic Cells and Fixed-Point Multiplication Circuits

Datla, Satyendra; Thornton, Mitchell A.

doi:10.1109/ismvl.2010.32

Cited by 11 publications

(3 citation statements)

References 25 publications

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“…The proposed multiplication blocks utilize a total of 2548 CNTFETs transistors including 93 for FA1, 113 for FA2, 71 for HA, 39 for the sum, and 53 for the multipliers. The proposed plan occupies 66.05% less space than that of [20]. In the proposed scheme, for a 4 × 4 multiplication operation, we should consider the delay of the eight multiplication blocks, six full adders, five half adders, and one sum increasing the multiplication rate to 55.59% compared to that of the usual method as shown in Figure 10.…”

Section: Proposed Circuitsmentioning

confidence: 99%

Low energy and area efficient quaternary multiplier with carbon nanotube field effect transistors

2021

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In this study, new multiplier and adder method designs with multiplexers are proposed. The designs are based on quaternary logic and a carbon nanotube field‐effect transistor (CNTFET). The design utilizes 4 × 4 multiplier blocks. Applying specific rotational functions and unary operators to the quaternary logic reduced the power delay produced (PDP) circuit by 54% and 17.5% in the CNTFETs used in the adder block and by 98.4% and 43.62% in the transistors in the multiplier block, respectively. The proposed 4 × 4 multiplier also reduced the occupied area by 66.05% and increased the speed circuit by 55.59%. The proposed designs are simulated using HSPICE software and 32 nm technology in the Stanford Compact SPICE model for CNTFETs. The simulated results display a significant improvement in the fabrication, average power consumption, speed, and PDP compared to the current best‐performing techniques in the literature. The proposed operators and circuits are evaluated under various operating conditions, and the results demonstrate the stability of the proposed circuits.

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Section: Proposed Circuitsmentioning

confidence: 99%

Low energy and area efficient quaternary multiplier with carbon nanotube field effect transistors

2021

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“…MVL circuit design is based on multiple threshold design techniques and adjusting the threshold voltage of CNFETs is easily possible by changing the diameter of the nanotubes [11,12]. In recent years, some MOSFET and CNFET MVL circuits, have been presented for ternary and quaternary logic [10,11,[13][14][15][16][17][18][19][20][21]. However, they have some critical drawbacks such as using very large ohmic resistors [13,14], requiring obsolete depletion-mode MOSFET [15,[17][18][19][20], non-full swing nodes and limited fanout [21].…”

Section: Introductionmentioning

confidence: 99%

Energy Efficient Tri-State CNFET Ternary Logic Gates

Tabrizchi¹,

Sharifi²,

Badawy³

2018

Preprint

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Traditional silicon binary circuits continue to face challenges such as high leakage power dissipation and large area of interconnections. Multiple-Valued Logic (MVL) and nano-devices are two feasible solutions to overcome these problems. In this paper, we present a novel method to design ternary logic circuits based on Carbon Nanotube Field Effect Transistors (CNFETs). The proposed designs use the unique properties of CNFETs, e.g., adjusting the Carbon Nanotube (CNT) diameters to have the desired threshold voltage and have the same mobility of P-FET and N-FET transistors. Each of our designed logic circuits implements a logic function and its complementary via a control signal. Also, these circuits have a high impedance state which saves power while the circuits are not in use. We show a more detailed application of our approach by designing a two-digit adder-subtractor circuit. We simulate the proposed ternary circuits using HSPICE via standard 32nm CNFET technology. The simulation results indicate the correct operation of the designs under different process, voltage and temperature (PVT) variations. Moreover, we designed a two-digit adder/subtractor and a power efficient ternary logic ALU based on the proposed gates. Simulation results show that the two-digit adder/subtractor using our proposed gates has 12X and 5X lower power consumption and PDP (power delay product) respectively, compared to previous designs.

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“…These sets are listed below - From the above list, the first two sets are used in form-II and form-I of sum-of-products (SOP) expressions respectively. The third set can also be used as an alternative representation of form-I of SOP as shown in [15].…”

Section: Introductionmentioning

confidence: 99%

Optimization of sum of product expressions in a novel quaternary algebra

Das

Jahangir

Hasan

2014

2014 International Conference on Informatics, Electronics &Amp; Vision (ICIEV)

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In this work, several techniques for the optimization of expressions in a novel quaternary algebra are discussed thoroughly. This quaternary algebra, which can be used to implement any quaternary logic function, is closely related to Boolean algebra. A set of quaternary operators are defined and two ways to express any quaternary function mathematically are described. Finally, we have discussed several quaternary functions in which the rules of optimization are used to reduce the complexity of expressions. Since optimization can be done in both forms of SOP in this algebra, this new logic, with the rules of optimization, may be quite useful for efficient implementation of quaternary functions.

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Quaternary Voltage-Mode Logic Cells and Fixed-Point Multiplication Circuits

Cited by 11 publications

References 25 publications

Low energy and area efficient quaternary multiplier with carbon nanotube field effect transistors

Low energy and area efficient quaternary multiplier with carbon nanotube field effect transistors

Energy Efficient Tri-State CNFET Ternary Logic Gates

Optimization of sum of product expressions in a novel quaternary algebra

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