Quaternary Look-Up Tables Using Voltage-Mode CMOS Logic Design

Power and delay comparison of binary and quaternary arithmetic circuits

“…In our experiments, the implementation of binary and quaternary lookup tables were implemented by a set of multiplexers such as presented in [4] and illustrated in Figure 2. Figure 2(a) shows a binary 4-BLUT implementation (b = 2, |X| = k = 4, |C| = 16) where x i ∈ X are the inputs, c i ∈ C form the lookup table configuration and z is the output.…”

“…As proposed by Cunha et al [4] for a 0.18µm technology (V DD = 1.8V ), we decide to maintain the V DD voltage as the same voltage used in the binary representation. By maintaining the V DD voltage we avoid the power increase due to the V 2 DD effect.…”

“…This is explained by the fact that in modern million-gates FPGAs, as much as 90% of chip area is devoted to interconnections [4].…”

“…The benefits of this MVL methodology can be directly applied to the FPGA domain. A new FPGA structure was proposed in [4] where information is represented by quaternary values. A new quaternary logic cell was presented and results demonstrate interesting area and power reductions in comparison to equivalent binary structures.…”

“…Circuit implementations are based on lookup table (LUTs) as proposed by [4]. As a case study, we perform an analysis of ripple carry adders.…”