Quasi-SOI MOSFETs—A Promising Bulk Device Candidate for Extremely Scaled Era

Tian, Yu; Xiao, Han; Huang, Ru; Feng, Chuguang; Chan, Mansun; Chen, Baoqin; Wang, Runsheng; Zhang, Xing; Wang, Yangyuan

doi:10.1109/ted.2007.899401

Cited by 15 publications

(7 citation statements)

References 9 publications

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“…The self-heating effect can also be alleviated as the channel is directly connected with the substrate. Therefore, according to our previous works, [14][15][16] QSOI device has great potentials for high performance applications. It can be fabricated on bulk substrate with a process which is basically compatible with CMOS technology.…”

Section: Cell Structure and Operationmentioning

confidence: 97%

“…In our previous works, quasi-SOI (QSOI) structure was proposed and experimentally characterized for logic and analog/RF applications. [14][15][16] It can be fabricated on bulk substrate, and was demonstrated with very good short channel performance, alleviated self-heating effect, which is very promising for ultra-scaled generations. Based on this promising structure, in this work we propose a novel QSOI capacitorless DRAM cell on bulk substrate.…”

Section: Introductionmentioning

confidence: 99%

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High Density Capacitorless Dynamic Random Access Memory Cell with Quasi Silicon-on-Insulator Structure Based on Bulk Substrate

Tang¹,

Huang²,

Wu³

et al. 2010

Jpn. J. Appl. Phys.

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A novel quasi silicon-on-insulator (QSOI) capacitorless dynamic random access memory (DRAM) Cell with bulk substrate is proposed and investigated for the first time. The QSOI DRAM cell is based on the promising highly scalable QSOI device structure. The deep L-shape layer of proposed QSOI cell can provide isolation between adjacent cells along bit line, without increasing the cell area as the one transistor (1T) bulk capacitorless DRAM cell. The electrical performance of this structure is also studied and compared with 1T-bulk cell. Longer retention time and larger sensing margin can be achieved in the proposed QSOI cell, due to the suppressed leakage current. The results indicate that QSOI cell has great potentials for high density DRAM applications.

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Section: Cell Structure and Operationmentioning

confidence: 97%

Section: Introductionmentioning

confidence: 99%

High Density Capacitorless Dynamic Random Access Memory Cell with Quasi Silicon-on-Insulator Structure Based on Bulk Substrate

Tang¹,

Huang²,

Wu³

et al. 2010

Jpn. J. Appl. Phys.

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“…In addition, the self-heating effect and the coupling of the drain to channel from the buried oxide layer, as well as the threshold voltage adjustment are also issues of the UTB SOI devices [105−107] . A kind of new devices, named Quasi-SOI MOSFET is proposed to alleviate the above issues and will be discussed in the following part [108,109] .…”

Section: Non-classical Device Architecturesmentioning

confidence: 99%

“…To alleviate the above-mentioned problems of UTB SOI devices, a novel device structure named Quasi-SOI MOSFET was proposed [108,109] , as shown in Figure 6.1. The path of the drain-induced barrier lowering can be reduced by the "L-type" insulator surrounding the source and drain of quasi SOI MOSFET, while avoiding the complex process of shallow junction or elevated source/drain.…”

Section: Quasi-soi Devicesmentioning

confidence: 99%

Challenges of 22 nm and beyond CMOS technology

Huang

Kang

et al. 2009

Sci. China Ser. F-Inf. Sci.

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It is predicted that CMOS technology will probably enter into 22 nm node around 2012. Scaling of CMOS logic technology from 32 to 22 nm node meets more critical issues and needs some significant changes of the technology, as well as integration of the advanced processes. This paper will review the key processing technologies which can be potentially integrated into 22 nm and beyond technology nodes, including double patterning technology with high NA water immersion lithography and EUV lithography, new device architectures, high K/metal gate (HK/MG) stack and integration technology, mobility enhancement technologies, source/drain engineering and advanced copper interconnect technology with ultra-low-k process.

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“…A novel device structure named Quasi-SOI MOSFET was proposed to eliminate the potential weaknesses of UTB SOI MOSFET [13,14] , as shown in Figure 11. The path of the drain-induced barrier lowering can be reduced by the "L-type" insulator surrounding the source and drain of quasi SOI MOSFET, while avoiding the complex process of shallow junction or elevated source/drain.…”

Section: Novel Quasi-soi Mosfet For Scaled Cmosmentioning

confidence: 99%

Novel devices and process for 32 nm CMOS technology and beyond

Wang

Zhang

Liu

et al. 2008

Sci. China Ser. F-Inf. Sci.

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The development of next 32 nm generation and below needs innovations on not only device structures, but also fabrication techniques and material selections. Among those promising technologies, new gate structures as high-k gate dielectric and metal gate, strain channel carrier mobility enhancement technology, and novel non-planar MOSFET structures are all possible candidate technologies. In this paper, we will specify our discussion on the research progress of high-k-metal gate and non-planar MOSFET-technologies that are suitable to 32 nm technology node and beyond.

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Quasi-SOI MOSFETs—A Promising Bulk Device Candidate for Extremely Scaled Era

Cited by 15 publications

References 9 publications

High Density Capacitorless Dynamic Random Access Memory Cell with Quasi Silicon-on-Insulator Structure Based on Bulk Substrate

High Density Capacitorless Dynamic Random Access Memory Cell with Quasi Silicon-on-Insulator Structure Based on Bulk Substrate

Challenges of 22 nm and beyond CMOS technology

Novel devices and process for 32 nm CMOS technology and beyond

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