Novel devices and process for 32 nm CMOS technology and beyond

Wang, Yangyuan; Zhang, Xing; Liu, Xiaoyan; Huang, Ru

doi:10.1007/s11432-008-0071-8

Cited by 5 publications

(2 citation statements)

References 19 publications

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“…In addition, gate capacitance also increases significantly with OX scaling for superthreshold circuits. To reduce the increased gate leakage, a gate dielectric with higher dielectric constant is introduced below 45 nm [16]. However, due to lower DD , The effective gate capacitance of a transistor is dominated by intrinsic depletion and parasitic capacitances, which are strongly dependent on OX [17].…”

Section: Effect Of Oxide Thickness and Channel Length On Device Parammentioning

confidence: 99%

Optimization and Characterization of CMOS for Ultra Low Power Applications

Kafeel¹,

Pable²,

Hasan³

et al. 2015

Journal of Nanotechnology

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Aggressive voltage scaling into the subthreshold operating region holds great promise for applications with strict energy budget. However, it has been established that higher speed superthreshold device is not suitable for moderate performance subthreshold circuits. The design constraint for selectingVthandTOXis much more flexible for subthreshold circuits at low voltage level than superthreshold circuits. In order to obtain better performance from a device under subthreshold conditions, it is necessary to investigate and optimize the process and geometry parameters of a Si MOSFET at nanometer technology node. This paper calibrates the fabrication process parameters and electrical characteristics for n- and p-MOSFETs with 35 nm physical gate length. Thereafter, the calibrated device for superthreshold application is optimized for better performance under subthreshold conditions using TCAD simulation. The device simulated in this work shows 9.89% improvement in subthreshold slope and 34% advantage inION/IOFFratio for the same drive current.

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Section: Effect Of Oxide Thickness and Channel Length On Device Parammentioning

confidence: 99%

Optimization and Characterization of CMOS for Ultra Low Power Applications

Kafeel¹,

Pable²,

Hasan³

et al. 2015

Journal of Nanotechnology

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“…As technology advances, conventional planar devices face difficulties and challenges due to uncontrollable short-channel effects (SCEs) and excessive V t variation [1]. Multiple-gate (MG) MOSFETs have been regarded as a leading component because of their better control over SCEs [2][3][4][5]. Similar to planar devices, as the channel length decreases and before SCEs become intolerable, short-channel MG MOSFETs offer both speed and density advantages over their long-channel counterparts.…”

Section: Introductionmentioning

confidence: 99%

Nanoscale triple-gate FinFET design considerations based on an analytical model of short-channel effects

Xie

Liang

Wang

et al. 2014

Sci. China Inf. Sci.

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In this paper, a three-dimensional (3-D) analytical model for short-channel effects (SCEs) in a nanoscale triple-gate (TG) FinFET is derived based on solving a boundary value problem using the 3-D Poisson's equation. This model is validated using 3-D numerical simulations (TCAD Sentaurus). Results show that SCEs in a TG FinFET can be controlled by reducing either the fin thickness (D) or height (H). On the other hand, when fixing the drive capability of turn-on current, i.e. fixing the total width of the conductive channel, and changing the ratio of D and H, there exists a case where SCEs are worst, and SCEs can be reduced by either increasing or decreasing the ratio from the worst case. This SCEs model can be used to predict the minimum channel length (L min) of a device when D, H, and tox are fixed, while keeping SCEs at a tolerable level. Based on the analytical model, the insights into the physics of SCEs in nanoscale TG FinFET are discussed, and design considerations are investigated.

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