Quantifying atom-scale dopant movement and electrical activation in Si:P monolayers

Abstract

Advanced hydrogen lithography techniques and low-temperature epitaxial overgrowth enable the patterning of highly phosphorus-doped silicon (Si:P) monolayers (ML) with atomic precision. This approach to device fabrication has made Si:P monolayer systems a testbed for multiqubit quantum computing architectures and atomically precise 2-D superlattice designs whose behaviors are directly tied to the deterministic placement of single dopants. However, dopant segregation, diffusion, surface roughening, and defect formation during the encapsulation overgrowth introduce large uncertainties to the exact dopant placement and activation ratio. In this study, we develop a unique method by combining dopant segregation/diffusion models with sputter profiling simulation to monitor and control, at the atomic scale, dopant movement using room-temperature grown locking layers (LLs). We explore the impact of LL growth rate, thickness, rapid thermal annealing, surface accumulation, and growth front roughness on dopant confinement, local crystalline quality, and electrical activation within Si:P 2-D systems. We demonstrate that dopant movement can be more efficiently suppressed by increasing the LL growth rate than by increasing the LL thickness. We find that the dopant segregation length can be suppressed below a single Si lattice constant by increasing the LL growth rates at room temperature while maintaining epitaxy. Although dopant diffusivity within the LL is found to remain high (on the order of 10 cm s) even below the hydrogen desorption temperature, we demonstrate that exceptionally sharp dopant confinement with high electrical quality within Si:P monolayers can be achieved by combining a high LL growth rate with low-temperature LL rapid thermal annealing. The method developed in this study provides a key tool for 2-D fabrication techniques that require precise dopant placement to suppress, quantify, and predict a single dopant's movement at the atomic scale.

Valley interference and spin exchange at the atomic scale in silicon

“…In our work, the donors were found at different atomic planes, which we attribute to an annealing step at 600°C performed during sample fabrication in order to flatten the surface for tunnelling spectroscopy purposes. Experimental progress has been made to minimise the segregation of highly doped phosphorus monolayers 46,47 , which should be further reduced for single donors as segregation and diffusion constants strongly depend on dopant concentration 48 . Single donor segregation mechanisms are predicted to activate from 250°C 49 , which bulk donor qubit device fabrication can withstand 6 .…”

Atomic-scale control of tunneling in donor-based devices

“…We then saturation-dose the patterned device regions with PH 3 followed by a rapid thermal anneal at 350°C for 1 min to incorporate the P dopant atoms into the Si surface lattice sites while preserving the hydrogen resist to confine dopants within the patterned regions. The device is then epitaxially encapsulated with intrinsic Si by using an optimized locking-layer process to suppress dopant movement at the atomic scale during epitaxial overgrowth 12,14 . The sample is then removed from the UHV system and Ohmic-contacted with e-beam-defined palladium silicide contacts 15 .…”

“…In this study, we overcome previous challenges by uniquely combining hydrogen lithography that generates atomically abrupt device patterns 10,11 with recent progress in low-temperature epitaxial overgrowth using a locking-layer technique [12][13][14] and silicide electrical contact formation 15 to substantially reduce unintentional dopant movement. These advances have allowed us to demonstrate the exponential scaling of the tunneling resistance on the tunnel gap separation in a systematic and reproducible manner.…”

“…These advances have allowed us to demonstrate the exponential scaling of the tunneling resistance on the tunnel gap separation in a systematic and reproducible manner. We suppress unintentional dopant movement at the atomic scale using an optimized, room temperature grown locking layer, which not only locks the dopant position within lithographically defined regions during encapsulation, but also improves reproducibility since the critical first few layers are always grown at room temperature 12 . Furthermore, our recent development of a high-yield, low-temperature method for forming ohmic contact to burried atomic devices enables robust electrical characteriation of STM-patterned devices with minimum thermal impact on dopant confinement 15 .…”

Tailoring Unsymmetrical‐Coordinated Atomic Site in Oxide‐Supported Pt Catalysts for Enhanced Surface Activity and Stability

“…[ 1 ] Generally, the optimization of catalysts predominantly focuses on engineering local geometry and electronic environment around the metal sites to achieve maximum reactive activity and enhanced stability. [ 2 ] The support effect is thus considered as one of the most pivotal factors to regulate the catalytic performance. [ 3 ] Although some experimental studies show that metal monomers soft‐landed on oxide supports can function as active sites for many fundamental chemical reactions, these metal atoms usually possess high mobility over the support surface and tend to spontaneous diffusion and aggregation, resulting in the deterioration of catalysts property.…”