Quality of designs from an automatic logic generator (ALERT)

Friedman, T. D.; Yang, Sih-Chin

doi:10.1145/800160.805114

Cited by 10 publications

(4 citation statements)

References 11 publications

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“…For example, the ALERT system was validated on an existing design, the IBM 1800, and the implementation produced required 160% more circuits than the manual design [Fri70].…”

Section: Logic Synthesismentioning

confidence: 99%

A new look at logic synthesis

Darringer

Joyner

1988

Papers on Twenty-Five Years of Electronic Design Automation

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Despite many attempts to generate hardware implementations automatically from functional specifications, the literature does not record any commercial success. Previous efforts have dealt primarily with technology-independent primitives and have emphasized circuit minimization.However, larger scales of integration have made other design requirements and technology restrictions as important as circuit count, and have increased the cost of making an engineering change. Thus it is becoming increasingly important to insure that initial chip designs are correct.This paper outlines an investigation into the feasibility of logic synthesis in this new context. A system is described which will produce a naive implementation automatically from a functionai specification, and then will interact with the designer, allowing him to evaluate it with respect to these many factors, and to improve it incrementally by applying local transformations until it is acceptable for manufacture.The use of simple local transformations will insure correct implementations, will isolate technology-specific data, and will allow the total process to be applied to larger VLSI designs. This approach has been tested on the design of a single chip with encouraging results. A prototype synthesis system is now being used to perform further experiments. Logic SynthesisThe goal of logic synthesis is to accept functional specifications for a hardware unit and to generate automatically a detailed, technology-specific implementation comparable in quality to that of an experienced engineer. The nature of this problem depends on the level of the functional description, the set of implementation primitives, and the criteria of acceptability.Initially, we are examining a restricted form of synthesis. That is, we are concentrating on the problem of generating masterslice implementations from low-level register transfer specifications in which all memory elements are specified. The combinational network between the memory elements must be generated and the entire function must be implemented with primitives from a specified set. Further, the implementation must satisfy given performance requirements and technology restrictions.We hope to determine the feasibility of interactive synthesis in this context, and the applicability of techniques of program analysis and optimization.There has been much work on automating logic design and, although many effective tools have been developed to aid the implementer, synthesis is not considered commercially successful. Early work centered on developing algorithms for translating a boolean function into a minimum two-level network of boolean primitives.Extensions were developed for handling limited circuit fan-in and alternative cost functions [Bre72, Die7 I]. Because these algorithms search for minimal implementations they are necessarily exponential and require too much space and time to be used on most actual designs.Later efforts attempted to raise the level of specification. The DDL work at Wisconsin ID~168, Die71], APDL...

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“…For example, the ALERT system was validated on an existing design, the IBM 1800, and the implementation produced required 160% more circuits than the manual design [Fri70].…”

Section: Logic Synthesismentioning

confidence: 99%

A new look at logic synthesis

Darringer

Joyner

1988

Papers on Twenty-Five Years of Electronic Design Automation

View full text Add to dashboard Cite

show abstract

Section: Logic Synthesismentioning

confidence: 99%

“…The results were usually more expensive than manual implementations and did not take advantage of the target technology. For example, the ALERT system was validated on an existing design, the IBM 1800, and the implementation produced required 160% more circuits than the manual design [Fri70].In attempts to generate more efficient logic and to give the user more control over the implementation, other strategies were tried [Sch62, Mes68, Hi173]. These constrain the specification language so that there is nearly a one-to-one correspondence between the specification and the implementation.…”

mentioning

confidence: 99%

A new look at logic synthesis

Darringer

Joyner

1980

Proceedings of the Seventeenth Design Automation Conference on Design Automation - DAC '80

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Despite many attempts to generate hardware implementations automatically from functional specifications, the literature does not record any commercial success. Previous efforts have dealt primarily with technology-independent primitives and have emphasized circuit minimization. However, larger scales of integration have made other design requirements and technology restrictions as important as circuit count, and have increased the cost of making an engineering change. Thus it is becoming increasingly important to insure that initial chip designs are correct. This paper outlines an investigation into the feasibility of logic synthesis in this new context. A system is described which will produce a naive implementation automatically from a functional specification, and then will interact with the designer, allowing him to evaluate it with respect to these many factors, and to improve it incrementally by applying local transformations until it is acceptable for manufacture. The use of simple local transformations will insure correct implementations, will isolate technology-specific data, and will allow the total process to be applied to larger VLSI designs. This approach has been tested on the design of a single chip with encouraging results. A prototype synthesis system is now being used to perform further experiments. Logic SynthesisThe goal of logic synthesis is to accept functional specifications for a hardware unit and to generate automatically a detailed, technology-specific implementation comparable in quality to that of an experienced engineer. The nature of this problem depends on the level of the functional description, the set of implementation primitives, and the criteria of acceptability. Initially, we are examining a restricted form of synthesis. That is, we are concentrating on the problem of generating masterslice implementations from low-level register transfer specifications in which all memory elements are Permission to copy without fee all or part of this material is granted provided that the copies are not made or distributed for direct commercial advantage, the ACM copyright notice and the title of the publication and its date appear, and notice is given that copying is by permission of the Association for Computing Machinery. To copy otherwise, or to republish, requires a fee and/or specific permission. specified. The combinational network between the memory elements must be generated and the entire function must be implemented with primitives from a specified set. Further, the implementation must satisfy given performance requirements and technology restrictions. We hope to determine the feasibility of interactive synthesis in this context, and the applicability of techniques of program analysis and optimization.There has been much work on automating logic design and, although many effective tools have been developed to aid the implementer, synthesis is not considered commercially successful. Early work centered on developing algorithms for translating a boolean function into a minimum two-le...

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“…The results were usually more expen-sive than manual implementations and did not take advantage of the target technology. For example, the ALERT system was validated on an existing design, the IBM 1800, and the implementation produced required 160% more gates than the manual design [7].…”

Section: Introductionmentioning

confidence: 99%

Logic Synthesis Through Local Transformations

et al. 1981

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A logic designer today faces a growing number of design requirements and technology restrictions, brought about by increases in circuit density and processor complexity. At the same time, the cost of engineering changes has made the correctness of chip implementations more important, and minimization of circuit count less so. These factors underscore the need for increased automation of logic design. This paper describes an experimental system for synthesizing synchronous combinational logic. It allows a designer to start with a naive implementation produced automatically from a functional specification, evaluate it with respect to these many factors, and incrementally improve this implementation by applying local transformations until it is acceptable for manufacture. The use of simple local transformations in this system ensures correct implementations, isolates technology-specac data, and will allow the total process to be applied to larger, VLSI designs. The system has been used to synthesize masterslice chip implementations from functional specacations, and to remap implemented masterslice chips from one technology to another while preserving their functional behavior. Several tools have been developed at Carnegie-Mellon University to support the early part of the design cycle [ll-141. In one experiment [15] the CMU-DA (Carnegie-Mellon University-Design Automation) system was used to implement the data path portion of a Digital Equipment Corporation (DEC) PDP3/E. It began with a functional Copyright 1981 by International Business Machines Corporation. Copying is permitted without payment of royalty provided that (1) each reproduction is done without alteration and (2) the Journal reference and IBM copyright notice are included on the first page. 272 The title and abstract may be used without further permission in computer-based and other information-service systems. Permission to republish other excerpts should be obtained from the Editor.

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Quality of designs from an automatic logic generator (ALERT)

Cited by 10 publications

References 11 publications

A new look at logic synthesis

A new look at logic synthesis

A new look at logic synthesis

Logic Synthesis Through Local Transformations

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