Quadruple time redundancy adders [error correcting adder]

Abstract

This paper presents a concurrent error correcting adder design employing fault masking through a combination of time and hardware redundancy. This new method, Quadruple Time Redundancy, is compared with a non-redundant adder, a Triple Modular Redundancy adder, and a Time Shared Triple Modular Redundancy adder with respect to the hardware complexity and the delay for adders of various sizes. In comparison with Time Shared Triple Modular Redundancy to which it is most closely related, Quadruple Time Redundancy results in a 40% -55% reduction in hardware complexity while incurring a reasonable delay zncrease.

A novel low overhead fault tolerant Kogge-Stone adder using adaptive clocking

“…The fault corrupts the C 3 first (at k=2) and C 5 , C 7 next (at k=3). These faults corrupt the odd Sum outputs (i.e., Sum 3 Fig. 2 (a) A basic 8 …”

“…4, Sum 4 and Sum 6 are faulty in cycle-1 whereas other Sums are computed correctly. After right shifting the Sums in cycle-2 and re-computation, the correct computations (Sum 1 , Sum 3 (4) (1) …”

“…Therefore the entire addition requires three clock cycles. Since operand widths are usually divisible by four, Quaternary Time Redundancy (QTR) [3] adder is proposed to utilize this fact and improve the area/delay overhead compared to TSTMR. In this technique the operands are divided-byfour and one quarter is instantiated three times with a majority voter.…”

“…Therefore, stuck-at faults are tolerated at the cost of area/delay overhead (due to HC stage and multiplexers). Quadruple time redundancy [3] and triple modular redundancy [4] techniques have also been proposed in order to detect and correct errors at the cost large area overhead.…”

Self-Checking and Self-Diagnosing 32-bit Microprocessor Multiplier

“…The 16-bit blocks of the adder perform each operation twice, once with functional inputs and once with the same operands rotated. The operand rotating technique was further improved by Townsend et al [19] to reduce the area overhead. Mokrian et al propose a hybrid multiplier architecture [12].…”