A novel low overhead fault tolerant Kogge-Stone adder using adaptive clocking

Ghosh, Swaroop; Ndai, Patrick; Roy, Kaushik

doi:10.1145/1403375.1403462

Cited by 13 publications

(4 citation statements)

References 6 publications

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“…The naive approach to computational error correction is TMR [86], requiring over a 200% overhead in area and energy for single error correcting capability. Several techniques in the form of arithmetic codes such as AN codes [6,18,19,41,66,88], self-checking [30,33,44,[48][49][50]84], and self-correcting [15,20,26,37,45,55,62,63,74,83] adders and multipliers have since been devised. Orthogonally, proposals employ redundancy at a higher granularity, such as timing speculation (wherein error correction capability is limited to circuit timing violations) [16,23], partial pipeline replication [2], or checkpoint-rollback-recovery such as those in IBM Power8 processors [29].…”

Section: Related Workmentioning

confidence: 99%

Extending Moore’s Law via Computationally Error-Tolerant Computing

Deng

Srikanth

Hein

et al. 2018

ACM Trans. Archit. Code Optim.

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Dennard scaling has ended. Lowering the voltage supply (V dd) to sub-volt levels causes intermittent losses in signal integrity, rendering further scaling (down) no longer acceptable as a means to lower the power required by a processor core. However, it is possible to correct the occasional errors caused due to lower V dd in an efficient manner and effectively lower power. By deploying the right amount and kind of redundancy, we can strike a balance between overhead incurred in achieving reliability and energy savings realized by permitting lower V dd. One promising approach is the Redundant Residue Number System (RRNS) representation. Unlike other error correcting codes, RRNS has the important property of being closed under addition, subtraction and multiplication, thus enabling computational error correction at a fraction of an overhead compared to conventional approaches. We use the RRNS scheme to design a Computationally-Redundant, Energy-Efficient core, including the microarchitecture, Instruction Set Architecture (ISA) and RRNS centered algorithms. From This paper is an extension of "Computationally-Redundant Energy-Efficient Processing for Y'all (CREEPY)" [11]. This submission adds the following: (1) Correction factor analysis for RRNS signed arithmetic, including an improved correction factor computation for signed multiplication via an LUT based mechanism. (Section 4.8.5) (2) Design and evaluation of an efficient RRNS multiplier unit by using the index-sum technique, along with associated re-derivation of suitable RRNS bases. (Sections 4.4 and 4.5) (3) A novel adaptive check insertion strategy that leverages hardware/software runtime or compiler. (Section 4.6.3) (4) Impact of multi-domain voltage supply to further lower energy consumption. (Sections 4.7, 6.1 and 6.3) (5) Improved evaluation accuracy by simulating an LLC-main memory hierarchy instead of a perfect cache. (Section 5) (6) Energy limit analysis for binary, RNS and RRNS cores. (Section 6) These add significantly more than 30% new material and provide greater insight into RRNS core design. W.r.t. written content, every section has been revamped to better present the new findings above.

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Section: Related Workmentioning

confidence: 99%

Extending Moore’s Law via Computationally Error-Tolerant Computing

Deng

Srikanth

Hein

et al. 2018

ACM Trans. Archit. Code Optim.

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“…For the generator and propagator circuitry, time redundancy is used via rotated operands. Ghosh et al [21] apply temporal redundancy to the Kogge-Stone adder based on the observation that even and odd carries are independent. In their two cycle addition technique, first, one of the correct set of bits (even/odd) are computed and stored at output register.…”

Section: Micro-architectural / Isa Independent Techniquesmentioning

confidence: 99%

A Brief Survey of Non-Residue Based Computational Error Correction

Srikanth¹,

Deng²,

Conte³

2016

Preprint

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The idea of computational error correction has been around for over half a century. The motivation has largely been to mitigate unreliable devices, manufacturing defects or harsh environments, primarily as a mandatory measure to preserve reliability, or more recently, as a means to lower energy by allowing soft errors to occasionally creep. While residue codes have shown great promise for this purpose, there have been several orthogonal non-residue based techniques. In this article, we provide a high level outline of some of these non-residual approaches. OverviewWe first classify various approaches to computational error correction into two broad categories:1. Temporal Redundancy. This approach is based on the hypothesis that the probability of transient errors that occur at the same place to have temporal multiplicity is very low. In other words, a soft error occurs infrequently at the same device, and as such, repeated measurements in some manner would serve as an indicator to the correct computation.2. Spatial Redundancy. This approach is based on the hypothesis that the probability of multiple identical computations to all be in error at the same time is very low. In other words, by replicating a computation, any error in a small fraction of the replicas can be masked / overpowered by the other correct replicas.These principles, it turns out, are fundamental to any sort of error correction including computation (ex. arithmetic), storage (ex. memory) and transmission (ex. networking). Some proposals favor spatial redundancy over temporal redundancy, some vice versa, and some employ both, depending upon the target fault model and environment. Given a technique, it is relatively straightforward to determine presence of temporal and/or spatial redundancy, as such, we leave this to the interested reader.Von Neumann [1] was among the first to propose using redundant components to overcome the effects of defective devices. He introduced the now widely used technique of Triple Modular Redundancy (TMR), which essentially uses three devices instead of one and uses a majority voter to infer a correct output. To note here is that such a mechanism can correct a single error (meaning that at least two of the three devices are not in error), or detect most double errors (where at least

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“…12, the designers implemented a 64-bit fault tolerant Kogge-Stone Adder (KSA). The authors observed that the KSA is a highly regular structure, able to compute carries in parallel, and that odd and even carries are evaluated independently.…”

Section: Existing Defect Tolerance Approachesmentioning

confidence: 99%

Defect tolerant prefix adder design

2008

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This paper introduces a defect tolerant 64-bit Sklansky prefix adder, designed with the goal of increasing its reliability and extending its lifetime in the presence of hard faults. We consider defect tolerance for early transistor wear-out by exploring the design of fine-grained reconfigurable logic. The approach involves enabling spare processing elements to replace defective elements. Power gating techniques are used to disable faulty logic blocks and enable spare logic. Minimum sized transistors are used for spare processing elements to reduce area overhead, and simplify reconfiguration interconnect.The performance of the design is compared to a baseline, non-repairing design using the cost metrics of: area overhead, power consumption, and performance in the fault free and faulty case.

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A novel low overhead fault tolerant Kogge-Stone adder using adaptive clocking

Abstract: Abstract-

Cited by 13 publications

References 6 publications

Extending Moore’s Law via Computationally Error-Tolerant Computing

Extending Moore’s Law via Computationally Error-Tolerant Computing

A Brief Survey of Non-Residue Based Computational Error Correction

Defect tolerant prefix adder design

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