2019
DOI: 10.1109/tcsi.2018.2872507
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Quadruple Cross-Coupled Latch-Based 10T and 12T SRAM Bit-Cell Designs for Highly Reliable Terrestrial Applications

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Cited by 118 publications
(105 citation statements)
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“…The schematic of the QUCCE10T cell [21] is shown in FIGURE 2-(e). The QUCCE10T cell has four storage nodes A, Q, QN, and B.…”
Section: Previous Hardened Memory Cellsmentioning
confidence: 99%
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“…The schematic of the QUCCE10T cell [21] is shown in FIGURE 2-(e). The QUCCE10T cell has four storage nodes A, Q, QN, and B.…”
Section: Previous Hardened Memory Cellsmentioning
confidence: 99%
“…The schematic of the QUCCE12T cell [21] is shown in FIGURE 2-(f). It can be seen that the QUCCE12T cell uses two extra access transistors with respect to the QUCCE10T cell to improve performance.…”
Section: Previous Hardened Memory Cellsmentioning
confidence: 99%
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