PVD TiN metal gate MOSFETs on bulk silicon and fully depleted silicon-on-insulator (FDSOI) substrates for deep sub-quarter micron CMOS technology

A 2-D analytical threshold-voltage model for GeOI/GeON MOSFET with high-k gate dielectric

“…Otherwise, the device is denoted as 2-D short-channel device, for which the 2-D Poisson's equation in the x and y directions has to be solved to obtain the surface potential. At threshold voltage or in the sub-threshold regime, the mobile carrier charges in the channel and polysilicon-depletion effect of the gate electrode (if the gate electrode is polysilicon) [17,18] can be neglected. So, the 2-D Poisson's equation for the electric potential φ(x,y) in the gate dielectric, channel, buried insulator and substrate regions can be written as:…”

Two-dimensional analytical subthreshold model of graded channel DG FD SOI n-MOSFET with gate misalignment effect

“…In order to simplify the analysis, the polysilicon depletion effect [12][13][14] and the quantum effect [15][16][17] are not considered.…”

Influence of sidewall spacer on threshold voltage of MOSFET with high-k gate dielectric

“…1. For simplification, polysilicon depletion effect [7,8] and quantum effect [9,10] are neglected. So, the 2-D Poisson's equation in the channel region and gate dielectric region, and relevant boundary conditions can be written as where N A is doping concentration of p-type substrate; k oxand k si are permittivities of gate dielectric and substrate, respectively; L is channel length; x d is width of depletion region in substrate (x d is variable); T ox is gate-dielectric thickness; V g is gate voltage; V fb is flat-band voltage; g s (y) and g d (y) are the boundary conditions at the source/drain ends, respectively.…”