Pushing ASIC performance in a power envelope

Abstract

Power dissipation is becoming the most challenging design constraint in nanometer technologies. Among various design implementation schemes, standard cell ASICs offer the best power efficiency for high-performance applications. The flexibility of ASICs allow for the use of multiple voltages and multiple thresholds to match the performance of critical regions to their timing constraints, and minimize the power everywhere else. We explore the trade-off between multiple supply voltages and multiple threshold voltages in the optimization of dynamic and static power. The use of multiple supply voltages presents some unique physical and electrical challenges. Level shifters need to be introduced between the various voltage regions. Several level shifter implementations will be shown. The physical layout needs to be designed to ensure the efficient delivery of the correct voltage to various voltage regions. More flexibility can be gained by using appropriate level shifters. We will discuss optimization techniques such as clock skew scheduling which can be effectively used to push performance in a power neutral way.

A novel energy efficient voltage level shifter

“…The design proposed in [8] performs only up shift and the static power consumed is 6.4 nW with delay of 22ns using 90nm technology. The design proposed in [2] also performs only up shift and static power consumed is 6.6nW with delay of 18.4ns using 130nm technology. The design proposed in [5] also performs only up shift and the average power consumed is 90nW with delay of 10ns using 130nm technology.…”

“…The design proposed in [5] also performs only up shift and the average power consumed is 90nW with delay of 10ns using 130nm technology. The operating frequency used in designs [8], [2], and [3] is 1MHz. The design proposed in [5] also performs only up shift and the average power consumed is 58nW with delay of 1000ns using 350nm technology with operating frequency of 10 KHz.…”

“…Voltage islands, operating at different voltages means the two or more supply voltages can be maintained among multi cores or multi functional blocks or even dividing a single chip by isolating the integrated circuit into regions. The circuits that are on the discriminating path are influenced with higher VDD (VDDH) and the circuits which are off the discriminating path are influenced with lower VDD (VDDL) [3], [2] to decrease the power consumption, in additional high speed perceptive paths are controlled with higher VDD and low speed perceptive paths can be controlled with lower VDD because power consumption is directly proportional to the square of the supply voltage. A Level Shifter is required to interface both VDDH and VDDL circuits (two or more supply VDD systems).…”

Keeping hot chips cool

“…In addition, due to increasing variability in sub-90nm process, the variability in power dissipation has been a source of dropping yield, i.e., a significant portion of the yield is now power-limited in high-performance designs [5]. In order to continue the CMOS scaling, it is crucial to tame this exponential increase in power dissipation [2]. In this paper, we outline practical techniques that are used to reduce both leakage as well as active power in a standard-cell library based high-performance design flow.…”

A block-level optimization of comprehensive thermal-aware power management for SoC integration in nano-scale CMOS technology

“…Several power reduction techniques can be adopted for modern power management designs, such as dynamic voltage scaling (DVS) [2], clock gating [3], power gating [1,4], body bias [5][6][7], and voltage islands [8]. DVS and clock gating can effectively reduce dynamic power consumption, while power gating and reverse body bias reduce static leakage power.…”