Keeping hot chips cool

Abstract

With 90nm CMOS in production and 65nm testing in progress, power has been pushed to the forefront of design metrics. This paper will outline practical techniques that are used to reduce both leakage as well as active power in a standard-cell library based high-performance design flow. We will discuss the design and cost issues for using different power saving techniques such as: power gating to reduce leakage, multiple and hybrid threshold libraries for leakage reduction and multiple supply voltage based design. In addition techniques to reduce clock tree power will be presented as power consumed in clocks accounts for a significant portion of total chip power. Practical aspects of implementing these techniques will also be discussed.

Coarse‐grained reconfiguration: dataflow‐based power management

“…To keep hot chips cool, the more the integration on a single die the more holistic power minimisation approaches are required across the whole design stack [19]. The power‐aware approach we are presenting combines structural and dynamic aspects.…”

Placement techniques for the physical synthesis of nanometer-scale integrated circuits

“…For microprocessors, it is a well-known fact that the clock distribution network including the clocked elements (e.g. latches, flip-flops and macros) consumes a majority of the total dynamic power, because the clock network usually switches during every clock cycle [22,50]. Studies [20,55] have shown that the leaf level of the clock tree, i.e., nets driving the clocked elements (hereafter referred to as latches), is a major power consumer among the entire clock distribution network.…”

“…In being driven by this LCB. Results in [50] show that this design style can significantly reduce the capacitive load on the clock signals driven by the LCBs, and also improve timing.…”

“…However, the design style proposed in [50] requires the latches to be moved after clustering and LCB duplication. This requires a more sophisticated clock tree synthesis methodology as shown in Figure 5.…”

“…[50], Puri et al proposed a design style where the latches are placed quite close to their driving LCB and form a "latch huddle". This is illustrated inFigure 5.3, which shows one LCB (long red rectangle in the center), with a cluster of latches (small red rectangles) placed right next to the LCB.…”