Pulse Shape Measurements by On-Chip Sense Amplifiers of Single Event Transients Propagating Through a 90 nm Bulk CMOS Inverter Chain

Abstract

Single event transient (SET) pulse shapes caused by Au ions with an energy of 946 MeV were measured at the microprobe facility at GSI in Darmstadt. Using on-chip sense amplifiers, our novel approach allows observing SET pulse shapes at any interesting circuit node with negligible distortion. We were hence able to accurately trace the propagation of SET pulses through a 90 nm CMOS inverter chain.Index Terms-Analog on-chip measurement, heavy ions, microprobe, particle beams, position dependence, radiation effects in devices, radiation effects in ICs, sense amplifiers, single event effects, single event transient (SET), soft errors.

Experimental Validation of a Faithful Binary Circuit Model

“…For UMC-65, we resorted to Spice simulations of a 7-stage inverter chain from a standard cell library. In case of UMC-90, we relied on a custom ASIC described in [10] What makes this ASIC an ideal target for our experiments is the fact that all inverter outputs are connected to on-chip low-intrusive high-speed analog sense amplifiers, as shown in Fig. 5.…”

“…Independent power supplies and grounds for inverters and amplifiers facilitate measurements with different digital supply voltages VDD. According to [10], extensive simulations and measurements have revealed excellent measurement accuracy (within the linear bandwidth of the amplifiers).…”

“…Moreover, as we operate our inverter chains at their speed limits, we also employed dedicated experiments to validate the accuracy of (part of) our Spice simulations. For our validation measurements, we used a custom UMC-90 ASIC [10] containing an inverter chain monitored by low-intrusive high-speed on-chip analog amplifiers attached to a high-speed real-time oscilloscope. Comparing the measurement results with corresponding simulations (using the post-layout netlists extracted from the ASIC design) indeed showed a very good match.…”

A Faithful Binary Circuit Model

“…Moreover, the inverter chains were operated at their speed limits, we also conducted dedicated measurements to validate the accuracy of our Spice simulations: Comparing the measurement results with corresponding simulations (using the post-layout netlists extracted from the ASIC design) indeed showed a very good match. For all our measurements, we used a custom UMC-90 ASIC [21] containing an inverter chain monitored by low-intrusive high-speed on-chip analog amplifiers attached to a high-speed real-time oscilloscope.…”

A faithful binary circuit model with adversarial noise

“…We employ the same experimental setup as in [12], which uses UMC-90 nm and UMC-65 nm bulk CMOS 7-stage inverter chains as the primary targets. For UMC-65, we resorted to Spice simulations of a standard cell library implementation, for UMC-90, we relied on a custom ASIC [8]. The latter provides a 7-stage inverter chain built from 700 nm x 80 nm (W x L) pMOS and 360 nm x 80 nm nMOS transistors, with threshold voltages 0.29 V and 0.26 V, respectively, and a nominal supply voltage of V DD = 1 V. As all inverter outputs are connected to on-chip low-intrusive high-speed analog sense amplifiers (gain 0.15, -3 dB cutoff frequency 8.5 GHz, input load equivalent to 3 inverter inputs), see Fig.…”